Certain device-tree node properties of shared device-tree nodes are
different between the AM62P and J722S SoCs. To avoid overriding the
properties and to avoid redefining the nodes in the k3-{soc}-main.dtsi
having such SoC specific properties, move the properties to the SoC
specific k3-{soc}-main.dtsi files.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240615081600.3602462-9-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Update "k3-j722s.dtsi" to include "k3-am62p-j722s-common-{}".dtsi files in
order to reuse the nodes shared with AM62P. Also include the J722S specific
"k3-j722s-main.dtsi".
Since the J7 family of SoCs has the k3-{soc}.dtsi file organized as:
k3-{soc}.dtsi = CPU + Cache + CBASS-Ranges + "Peripheral-Includes"
switch the "k3-j722s.dtsi" file to the same convention.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240615081600.3602462-5-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
J722S does not pin out all of the GPIO same as AM62P and have
more number of GPIO on the main_gpio1 instance. Fix the GPIO
count on both instances by overriding the ti,ngpio property.
Fixes: ea55b9335a ("arm64: dts: ti: Introduce J722S family of SoCs")
More details at J722S/AM67 Datasheet (Section 5.3.11, GPIO):
https://www.ti.com/lit/ds/symlink/am67.pdf
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20240507103332.167928-1-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The J722S is a family of application processors built for Automotive and
Linux Application development. J722S family of SoCs is a superset of the
AM62P SoC family and shares similar memory map, thus the nodes are being
reused from AM62P includes instead of duplicating the definitions.
Some highlights of J722S SoC (in addition to AM62P SoC features) are:
* Two Cortex-R5F for Functional Safety or general-purpose usage and
two C7x floating point vector DSP with Matrix Multiply Accelerator
for deep learning.
* Vision Processing Accelerator (VPAC) with image signal processor
and Depth and Motion Processing Accelerator (DMPAC).
* 7xUARTs, 3xSPI, 5xI2C, 2xUSB2, 2xCAN-FD, 3xMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 5xMcASP for audio,
4xCSI-RX for Camera, 1 PCIe Gen3 controller, USB3.0 eCAP/eQEP,
ePWM, among other peripherals.
For those interested, more details about this SoC can be found in the
Technical Reference Manual here:
https://www.ti.com/lit/zip/sprujb3
Co-developed-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20240206100608.127702-3-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
