According to latest errata of J721e [1], HS400 mode is not supported
in MMCSD0 subsystem (i2024) and SDR104 mode is not supported in MMCSD1/2
subsystems (i2090). Therefore, replace mmc-hs400-1_8v with mmc-hs200-1_8v
in MMCSD0 subsystem and add a sdhci mask to disable SDR104 speed mode.
Also, update the itap delay values for all the MMCSD subsystems according
the latest J721e data sheet[2]
[1] - https://www.ti.com/lit/er/sprz455/sprz455.pdf
[2] - https://www.ti.com/lit/ds/symlink/tda4vm.pdf
Fixes: cd48ce86a4 ("arm64: dts: ti: k3-j721e-common-proc-board: Add support for SD card UHS modes")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210305054104.10153-1-a-govindraju@ti.com
Add the DT nodes for the ICSSG0 and ICSSG1 processor subsystems that are
present on the K3 J721E SoCs. The two ICSSGs are identical to each other
for the most part, with the ICSSG1 supporting slightly enhanced features
for supporting SGMII PRU Ethernet. Each ICSSG instance is represented by
a PRUSS subsystem node and other child nodes. These nodes are enabled by
default.
The ICSSGs on K3 J721E SoCs are revised versions of the ICSSG on the first
AM65x SR1.0 SoCs. The PRU IRAMs are slightly smaller, and the IP includes
two new auxiliary PRU cores called Tx_PRUs. The Tx_PRUs have 6 KB of IRAMs
and leverage the same host interrupts as the regular PRU cores. All The
ICSSG host interrupts intended towards the main Arm core are also shared
with other processors on the SoC, and can be partitioned as per system
integration needs.
The ICSSG subsystem node contains the entire address space. The various
sub-modules of the ICSSG are represented as individual child nodes (so
platform devices themselves) of the PRUSS subsystem node. These include
the two PRU cores, two RTU cores, two Tx_PRU cores and the interrupt
controller. All the Data RAMs are represented within a child node of
its own named 'memories' without any compatible. The Real Time Media
Independent Interface controller (MII_RT), the Gigabit capable MII_G_RT
and the CFG sub-module are represented as syscon nodes. The ICSSG CFG
sub-module provides two internal clock muxes, and these are represented
as children of the CFG child node 'clocks' by the 'coreclk-mux' and
iepclk-mux' clk nodes. The default parents for these mux clocks are also
defined using the assigned-clock-parents property.
The DT nodes use all standard properties. The regs property in the
PRU/RTU/Tx_PRU nodes define the addresses for the Instruction RAM, the
Debug and Control sub-modules for that PRU core. The firmware for each
PRU/RTU/Tx_PRU core is defined through a 'firmware-name' property.
The default names for the firmware images for each PRU, RTU and Tx_PRU
cores are defined as follows (these can be adjusted either in derivative
board dts files or through sysfs at runtime if required):
ICSSG0 PRU0 Core : j7-pru0_0-fw ; PRU1 Core : j7-pru0_1-fw
ICSSG0 RTU0 Core : j7-rtu0_0-fw ; RTU1 Core : j7-rtu0_1-fw
ICSSG0 Tx_PRU0 Core : j7-txpru0_0-fw ; Tx_PRU1 Core : j7-txpru0_1-fw
ICSSG1 PRU0 Core : j7-pru1_0-fw ; PRU1 Core : j7-pru1_1-fw
ICSSG1 RTU0 Core : j7-rtu1_0-fw ; RTU1 Core : j7-rtu1_1-fw
ICSSG1 Tx_PRU0 Core : j7-txpru1_0-fw ; Tx_PRU1 Core : j7-txpru1_1-fw
Note:
1. The ICSSG INTC on J721E SoCs share all the host interrupts with other
processors, so use the 'ti,irqs-reserved' property in derivative board
dts files _if_ any of them should not be handled by the host OS.
2. There are few more sub-modules like the Industrial Ethernet Peripherals
(IEPs), MDIO, PWM, UART that do not have bindings and so will be added
in the future.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20210304160712.8452-3-s-anna@ti.com
Now the dtbs_check produces below warnings
sdhci@4f80000: clock-names:0: 'clk_ahb' was expected
sdhci@4f80000: clock-names:1: 'clk_xin' was expected
$nodename:0: 'sdhci@4f80000' does not match '^mmc(@.*)?$'
Fix above warnings by updating mmc DT definitions to follow
sdhci-am654.yaml bindings:
- rename sdhci dt nodes to 'mmc@'
- swap clk_xin/clk_ahb clocks, the clk_ahb clock expected to be defined
first
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20210115193016.5581-1-grygorii.strashko@ti.com
Cadence IP in J721E supports a maximum of 32 outbound regions. However
commit 4e5833884f ("arm64: dts: ti: k3-j721e-main: Add PCIe device
tree nodes") incorrectly added this as 16 outbound regions. Now that
"cdns,max-outbound-regions" is an optional property with default value
as 32, remove "cdns,max-outbound-regions" from endpoint DT node.
(Since this doesn't impact existing functionality, it need not be
backported to older kernels).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20210105151421.23237-2-kishon@ti.com
Add support for UHS modes for the SD card connected at sdhci1. This
involves adding regulators for voltage switching and power cycling the
SD card and removing the no-1-8-v property.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20201129175223.21751-3-nsekhar@ti.com
There are couple of places where INTA interrupt controller
lacks #interrupt-cells property. This leads to warnings of
the type:
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi:147.51-156.5: Warning (interrupt_provider): /bus@100000/main-navss/interrupt-controller@33d00000: Missing #interrupt-cells in interrupt provider
when building TI device-tree files with W=2 warning level.
Fix these.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Link: https://lore.kernel.org/r/20201127210128.9151-1-nsekhar@ti.com
The default state of a device tree node is "okay". There is no specific
use of explicitly adding status = "okay" in the SoC dtsi.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Link: https://lore.kernel.org/r/20201113211826.13087-4-nm@ti.com
The device tree standard states that when the status property is
not present under a node, the okay value is assumed. There are many
reasons for doing the same, the number of strings in the device
tree, default power management functionality, etc. are a few of the
reasons.
In general, after a few rounds of discussions [1] there are few
options one could take when dealing with SoC dtsi and board dts
a. SoC dtsi provide nodes as a super-set default (aka enabled) state and
to prevent messy board files, when more boards are added per SoC, we
optimize and disable commonly un-used nodes in board-common.dtsi
b. SoC dtsi disables all hardware dependent nodes by default and board
dts files enable nodes based on a need basis.
c. Subjectively pick and choose which nodes we will disable by default
in SoC dtsi and over the years we can optimize things and change
default state depending on the need.
While there are pros and cons on each of these approaches, the right
thing to do will be to stick with device tree default standards and
work within those established rules. So, we choose to go with option
(a).
Lets cleanup defaults of j721e SoC dtsi before this gets more harder
to cleanup later on and new SoCs are added.
The only functional difference between the dtb generated is
status='okay' is no longer necessary for mcasp10 and depends on the
default state.
NOTE: There is a known risk of omission that new board dts developers
might miss reviewing both the board schematics in addition to all the
DT nodes of the SoC when setting appropriate nodes status to disable
or reserved in the board dts. This can expose issues in drivers that
may not anticipate an incomplete node (example: missing appropriate
board properties) being in an "okay" state. These cases are considered
bugs and need to be fixed in the drivers as and when identified.
[1] https://lore.kernel.org/linux-arm-kernel/20201027130701.GE5639@atomide.com/
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Cc: Jyri Sarha <jsarha@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20201113211826.13087-3-nm@ti.com
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT nodes for these two MAIN domain R5F cluster/subsystems,
the two R5F cores are each added as child nodes to the corresponding
main cluster node. Both the clusters are configured to run in LockStep
mode by default, with the ATCMs enabled to allow the R5 cores to execute
code from DDR with boot-strapping code from ATCM. The inter-processor
communication between the main A72 cores and these processors is
achieved through shared memory and Mailboxes.
The following firmware names are used by default for these cores, and
can be overridden in a board dts file if needed:
MAIN R5FSS0 Core0: j7-main-r5f0_0-fw (both in LockStep and Split modes)
MAIN R5FSS0 Core1: j7-main-r5f0_1-fw (needed only in Split mode)
MAIN R5FSS1 Core0: j7-main-r5f1_0-fw (both in LockStep and Split modes)
MAIN R5FSS1 Core1: j7-main-r5f1_1-fw (needed only in Split mode)
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20201029033802.15366-7-s-anna@ti.com
Add PCIe device tree nodes (both RC and EP) for the four
PCIe instances here.
Also add the missing translations required in the "ranges"
DT property of cbass_main to access all the four PCIe
instances.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20200914152115.1788-2-kishon@ti.com
We intend to use one header file for SERDES MUX for all
TI SoCs so rename the header file.
The exsting macros are too generic. Prefix them with SoC name.
While at that, add the missing configurations for completeness.
Fixes: b766e3b0d5 ("arm64: dts: ti: k3-j721e-main: Add system controller node and SERDES lane mux")
Reported-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/20200918165930.2031-1-rogerq@ti.com
Building with W=2 throws up a bunch of easy to fixup warnings..
node_name_chars_strict is one of them.. Knock those out.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200903130015.21361-9-nm@ti.com
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.
The following firmware name is used by default for the C71x core,
and can be overridden in a board dts file if desired:
C71x_0 DSP: j7-c71_0-fw
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-6-s-anna@ti.com
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.
The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
C66x_0 DSP: j7-c66_0-fw
C66x_1 DSP: j7-c66_1-fw
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-3-s-anna@ti.com
The USB controllers can be connected to one of the 2 SERDESes
using a MUX. Add a MUX controller node fot that.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The system controller node manages the CTRL_MMR0 region.
Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add DT nodes for all instances of WIZ and SERDES modules.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The preferable name for gic-its is msi-controller, so rename it to fix
dtbs_check warning:
k3-j721e-common-proc-board.dt.yaml: interrupt-controller@1800000:
gic-its@1820000: False schema does not allow {'compatible':
['arm,gic-v3-its'], 'reg': [[0, 25296896, 0, 65536]],
'socionext,synquacer-pre-its': [[16777216, 4194304]], 'msi-controller':
True, '#msi-cells': [[1]]}
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Rename smmu node to iommu to fix dtbs_check warning:
k3-j721e-common-proc-board.dt.yaml: smmu@36600000: $nodename:0: 'smmu@36600000' does not match '^iommu@[0-9a-f]*'
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This is the set of device tree changes, mostly covering new
hardware support, with 577 patches touching a little over 500
files.
There are five new Arm SoCs supported in this release, all of
them for existing SoC families:
- Realtek RTD1195, RTD1395 and RTD1619 -- three SoCs used in
both NAS devices and Android Set-top-box designs, along
with the "Horseradish", "Lion Skin" and "Mjolnir" reference
platforms; the Mele X1000 and Xnano X5 set-top-boxes and
the Banana Pi BPi-M4 single-board computer.
- Renesas RZ/G1H (r8a7742) -- a high-end 32-bit industrial SoC
and the iW-RainboW-G21D-Qseven-RZG1H board/SoM
- Rockchips RK3326 -- low-end 64-bit SoC along with the
Odroid-GO Advance game console
Newly added machines on already supported SoCs are:
- AMLogic S905D based Smartlabs SML-5442TW TV box
- AMLogic S905X3 based ODROID-C4 SBC
- AMLogic S922XH based Beelink GT-King Pro TV box
- Allwinner A20 based Olimex A20-OLinuXino-LIME-eMMC SBC
- Aspeed ast2500 based BMCs in Facebook x86 "Yosemite V2"
and YADRO OpenPower P9 "Nicole"
- Marvell Kirkwood based Check Point L-50 router
- Mediatek MT8173 based Elm/Hana Chromebook laptops
- Microchip SAMA5D2 "Industrial Connectivity Platform"
reference board
- NXP i.MX8m based Beacon i.MX8m-Mini SoM development kit
- Octavo OSDMP15x based Linux Automation MC-1 development board
- Qualcomm SDM630 based Xiaomi Redmi Note 7 phone
- Realtek RTD1295 based Xnano X5 TV Box
- STMicroelectronics STM32MP1 based Stinger96 single-board
computer and IoT Box
- Samsung Exynos4210 based based Samsung Galaxy S2 phone
- Socionext Uniphier based Akebi96 SBC
- TI Keystone based K2G Evaluation board
- TI am5729 based Beaglebone-AI development board
Include device descriptions for additional hardware support in existing
SoCs and machines based on all major SoC platforms:
- AMlogic Meson
- Allwinner sunxi
- Arm Juno/VFP/Vexpress/Integrator
- Broadcom bcm283x/bcm2711
- Hisilicon hi6220
- Marvell EBU
- Mediatek MT27xx, MT76xx, MT81xx and MT67xx
- Microchip SAMA5D2
- NXP i.MX6/i.MX7/i.MX8 and Layerscape
- Nvidia Tegra
- Qualcomm Snapdragon
- Renesas r8a77961, r8a7791
- Rockchips RK32xx/RK33xx
- ST-Ericsson ux500
- STMicroelectronics SMT32
- Samsung Exynos and S5PV210
- Socionext Uniphier
- TI OMAP5/DRA7 and Keystone
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM devicetree updates from Arnd Bergmann:
"This is the set of device tree changes, mostly covering new hardware
support, with 577 patches touching a little over 500 files.
There are five new Arm SoCs supported in this release, all of them for
existing SoC families:
- Realtek RTD1195, RTD1395 and RTD1619 -- three SoCs used in both NAS
devices and Android Set-top-box designs, along with the
"Horseradish", "Lion Skin" and "Mjolnir" reference platforms; the
Mele X1000 and Xnano X5 set-top-boxes and the Banana Pi BPi-M4
single-board computer.
- Renesas RZ/G1H (r8a7742) -- a high-end 32-bit industrial SoC and
the iW-RainboW-G21D-Qseven-RZG1H board/SoM
- Rockchips RK3326 -- low-end 64-bit SoC along with the Odroid-GO
Advance game console
Newly added machines on already supported SoCs are:
- AMLogic S905D based Smartlabs SML-5442TW TV box
- AMLogic S905X3 based ODROID-C4 SBC
- AMLogic S922XH based Beelink GT-King Pro TV box
- Allwinner A20 based Olimex A20-OLinuXino-LIME-eMMC SBC
- Aspeed ast2500 based BMCs in Facebook x86 "Yosemite V2" and YADRO
OpenPower P9 "Nicole"
- Marvell Kirkwood based Check Point L-50 router
- Mediatek MT8173 based Elm/Hana Chromebook laptops
- Microchip SAMA5D2 "Industrial Connectivity Platform" reference
board
- NXP i.MX8m based Beacon i.MX8m-Mini SoM development kit
- Octavo OSDMP15x based Linux Automation MC-1 development board
- Qualcomm SDM630 based Xiaomi Redmi Note 7 phone
- Realtek RTD1295 based Xnano X5 TV Box
- STMicroelectronics STM32MP1 based Stinger96 single-board computer
and IoT Box
- Samsung Exynos4210 based based Samsung Galaxy S2 phone
- Socionext Uniphier based Akebi96 SBC
- TI Keystone based K2G Evaluation board
- TI am5729 based Beaglebone-AI development board
Include device descriptions for additional hardware support in
existing SoCs and machines based on all major SoC platforms:
- AMlogic Meson
- Allwinner sunxi
- Arm Juno/VFP/Vexpress/Integrator
- Broadcom bcm283x/bcm2711
- Hisilicon hi6220
- Marvell EBU
- Mediatek MT27xx, MT76xx, MT81xx and MT67xx
- Microchip SAMA5D2
- NXP i.MX6/i.MX7/i.MX8 and Layerscape
- Nvidia Tegra
- Qualcomm Snapdragon
- Renesas r8a77961, r8a7791
- Rockchips RK32xx/RK33xx
- ST-Ericsson ux500
- STMicroelectronics SMT32
- Samsung Exynos and S5PV210
- Socionext Uniphier
- TI OMAP5/DRA7 and Keystone"
* tag 'arm-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (564 commits)
ARM: dts: keystone: Rename "msmram" node to "sram"
arm: dts: mt2712: add uart APDMA to device tree
arm64: dts: mt8183: add mmc node
arm64: dts: mt2712: add ethernet device node
arm64: tegra: Make the RTC a wakeup source on Jetson Nano and TX1
ARM: dts: mmp3: Add the fifth SD HCI
ARM: dts: berlin*: Fix up the SDHCI node names
ARM: dts: mmp3: Fix USB & USB PHY node names
ARM: dts: mmp3: Fix L2 cache controller node name
ARM: dts: mmp*: Fix up encoding of the /rtc interrupts property
ARM: dts: pxa*: Fix up encoding of the /rtc interrupts property
ARM: dts: pxa910: Fix the gpio interrupt cell number
ARM: dts: pxa3xx: Fix up encoding of the /gpio interrupts property
ARM: dts: pxa168: Fix the gpio interrupt cell number
ARM: dts: pxa168: Add missing address/size cells to i2c nodes
ARM: dts: dove: Fix interrupt controller node name
ARM: dts: kirkwood: Fix interrupt controller node name
arm64: dts: Add SC9863A emmc and sd card nodes
arm64: dts: Add SC9863A clock nodes
arm64: dts: mt6358: add PMIC MT6358 related nodes
...
Add DT node for Main NAVSS CPTS module.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add the nodes for McASP 0-11 and keep them disabled because several
required properties are not present as they are board specific.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add the ringacc and udmap nodes for main and mcu NAVSS.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Secure proxy (NAVSS0_SEC_PROXY0) and smmu (NAVSS0_TCU) is part of the
Navigator Subsystem.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
NAVSS is a subsystem containing different IPs, it is not really a bus.
Change the compatible from "simple-bus" to "simple-mfd" to reflect that.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add power-domains entry for smmu, so that the it is accessible as long
as the driver is active. Without this device shutdown is throwing the
below warning:
"[ 44.736348] arm-smmu-v3 36600000.smmu: failed to clear cr0"
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
J721e has 2 USB super-speed controllers add them.
The USB2 PHY doesn't need any configuration.
USB3 PHY needs to be implemented using the Cadence
Sierra PHY. This support will be added later.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add nodes for the 3 SDHCI instances present on TI's J721E device.
instance 0 supports HS400 (8 bit bus widht, DDR, 400 MBps)
while instances 1 and 2 support SDR104 (4 bit width, SDR, 100 MBps) as
their highest speed modes. Currently, only High speed (50 MHz clock) has
been enabled.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The J721E Main NavSS block contains a Mailbox IP instance with
multiple clusters. Each cluster is equivalent to an Mailbox IP
instance on OMAP platforms.
Add all the Mailbox clusters as their own nodes under the MAIN
NavSS cbass_main_navss interconnect node instead of creating an
almost empty parent node for the new K3 mailbox IP and the clusters
as its child nodes. All these nodes are enabled by default in the
base dtsi file, but any cluster that does not define any child
sub-mailbox nodes should be disabled in the corresponding board
dts files.
NOTE:
The NavSS only has a limited number of interrupts, so none of the
interrupts generated by a Mailbox IP are added by default. Only
the needed interrupts that are targeted towards the A72 GIC will
have to be added later on in the board dts files alongside the
corresponding sub-mailbox child nodes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The gic-its node unit-address has an additional zero compared
to the actual reg value. Fix it.
Fixes: 2d87061e70 ("arm64: dts: ti: Add Support for J721E SoC")
Reported-by: Robert Tivy <rtivy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The Main NavSS block on J721E SoCs contains a HwSpinlock IP instance that
is same as the IP on AM65x SoCs and similar to the IP on some OMAP SoCs.
Add the DT node for this on J721E SoCs. The node is present within the
Main NavSS block, and is added as a child node under the cbass_main_navss
interconnect node.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
There are 8 instances of gpio modules in main domain divided into 2 groups:
- Group1: gpio0, gpio2, gpio4, gpio6
- Group2: gpio1, gpio3, gpio5, gpio7
Groups are created to provide protection between two different processor
virtual worlds. There are x gpio lines coming out of each group. Each module
in a group has equal x gpio lines pinned out. There is a top level mux for
selecting the module instance for each pin coming out of group. Exactly
one module can be selected to control the corresponding pin. This muxing
can be controlled along the pad mux configuration registers.
Group1 pins out 128 lines(8 banks). Group 2 pins out 36 lines(2 banks).
Add DT nodes for each module instance in the main domain. Users should
make sure that correct gpio instance is selected in their pad configuration.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Update the power-domain cells to 2 and mark all devices as
exclusive. Main uart 0 is the debug console for processor boards
and it is used by different software entities like u-boot, atf,
linux simultaneously. So just mark main_uart0 as shared device
for common processor board.
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Main domain in J721E has the following interrupt controller instances:
- Main Domain GPIO Interrupt router connected to gpio in main domain.
- Under the Main Domain Navigator Subsystem(NAVSS)
- Main Navss Interrupt Router connected to main navss inta and mailboxes.
- Main Navss Interrupt Aggregator connected to main domain UDMASS
Add DT nodes for the interrupt controllers available in main domain.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add the Interrupt controller node for the Interrupt Router present within
the Main NavSS module. This Interrupt Router can route 192 interrupts to
the GIC_SPI in 3 sets of 64 interrupts each. Note that the last set is
reserved for the host ID A72_3 for hypervisor usecases, so the node is
added only with 2 sets for the Linux kernel context (host id A72_2). This
is specified through the ti,sci-rm-range-girq property.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
