Remove "ti,(rx|tx)-fifo-depth" properties which are both unused in the
kernel and undocumented. Most likely they are leftovers from downstream.
There are similar properties, but DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
represents the default value so adding them is not necessary.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241115193359.3618020-1-robh@kernel.org
Signed-off-by: Nishanth Menon <nm@ti.com>
External interfaces should be disabled at the SoC DTSI level, since
the node is incomplete. Disable Ethernet switch and ports in SoC DTSI
and enable them in the board DTS. If the board DTS includes a SoM DTSI
that completes the node description, enable the Ethernet switch and
ports in SoM DTSI.
Reflect this change in SoM DTSIs by removing ethernet port disable.
Signed-off-by: Logan Bristol <logan.bristol@utexas.edu>
Acked-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Acked-by: Josua Mayer <josua@solid-run.com>
Link: https://lore.kernel.org/r/20240809135753.1186-1-logan.bristol@utexas.edu
Signed-off-by: Nishanth Menon <nm@ti.com>
MIT license was added to the AM64x SoC DTSIs in commit 6248b20e32
("arm64: dts: ti: k3-am64: Add MIT license along with GPL-2.0"). Apply
the same license change to the TQMa64xxL SoM and MBaX4XxL baseboard
Device Trees.
The copyright year is updated to indicate the license change.
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/20240625110244.9881-1-matthias.schiffer@ew.tq-group.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Remove DLL properties which are not applicable for soft PHYs
since these PHYs do not have a DLL to enable.
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com> # Verdin AM62
Signed-off-by: Judith Mendez <jm@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20240213235701.2438513-7-jm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
SDHCI nodes defined in the top-level AM64 SoC dtsi files are incomplete
and will not be functional unless they are extended.
As the attached SD/eMMC is only known about at the board integration level,
these nodes should only be enabled when provided with this information.
Disable the SDHCI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20231117163339.89952-2-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The pin headers X41 and X42 do not have a fixed function. All of these
pins can be assigned to PRG0, but as a default, it makes more sense to
configure them as simple GPIOs, as the MBaX4XxL is a starterkit/evaluation
mainboard.
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/77c30081154774ce31fc4306474a3afa52b07753.1695901360.git.matthias.schiffer@ew.tq-group.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
TSCADC nodes defined in the top-level AM64 SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux and/or
device information.
Disable the TSCADC nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230810003814.85450-14-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
