The assigned-clocks and assigned-clock-rates properties were moved from
the scmi_clk node onto cpu nodes in commit
87810bda8a ("arm64: dts: rockchip: Fix SCMI assigned clocks on rk3588s")
During review of v1 of that patch set, the following comment was made:
why aren't you using OPP tables to define CPU frequencies.
Assigned-clocks looks like a temporary hack because you haven't
done proper OPP tables.
Some time later, proper OPP tables for rk3588 were added in commit
276856db91 ("arm64: dts: rockchip: Add OPP data for CPU cores on RK3588")
So this 'temporary hack' is no longer needed.
Dropping it fixes the following dtb validation issues:
cpu@0: Unevaluated properties are not allowed
('assigned-clock-rates', 'assigned-clocks' were unexpected)
cpu@400: Unevaluated properties are not allowed
('assigned-clock-rates', 'assigned-clocks' were unexpected)
cpu@600: Unevaluated properties are not allowed
('assigned-clock-rates', 'assigned-clocks' were unexpected)
Link: https://lore.kernel.org/linux-rockchip/CAL_JsqL_EogoKOQ1xwU75=rJSC4o7yV3Jej4vadtacX2Pt3-hw@mail.gmail.com/
Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
Link: https://lore.kernel.org/r/20250519101909.62754-1-didi.debian@cknow.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The RK3588 comes with two DSI2 controllers based on a new Synopsis IP.
Add the necessary nodes for them.
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> # RK3588 EVB1
Link: https://lore.kernel.org/r/20250226140942.3825223-3-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the two MIPI-DC-phy nodes to the RK3588, that will be used by the
DSI2 controllers and hopefully in some future also for camera input.
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> # RK3588 EVB1
Link: https://lore.kernel.org/r/20250226140942.3825223-2-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
0x0 to 0xf0000000 are SDRAM memory areas where 0x10f000 is located.
So move the SHMEM memory of arm_scmi to the reserved memory node.
Fixes: c9211fa260 ("arm64: dts: rockchip: Add base DT for rk3588 SoC")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250401090009.733771-2-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
With the binding header now providing the SCMI_SRST_H_TRNG_NS constant,
switch back to it from the temporary numeric value.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
There is new support for additional on-chip devices on Apple, Mediatek,
Renesas, Rockchip, Samsung, Google, TI, ST, Nvidia and Amlogic devices.
The Arm Morello reference platform gets a devicetree for booting in
normal aarch64 mode. The hardware supports experimental CHERI support,
which requires a modified kernel.
The AMD (formerly Xilinx) Versal NET SoC gets added, this is a combined
FPGA with Cortex-A78 CPUs in a SoC.
Six new ST STM32MP2 SoC variants are added. Like the earlier STM32MP25,
the MP211, MP213, MP215, MP231, MP233 and MP235 models are based on one
or two Cortex-A35 cores but each feature a different set of I/O devices.
Mediatek MT8370 is a minor variation of MT8390 with fewer CPU and
GPU cores
Apple T2 is the baseboard management controller on earlier Intel CPU
based Macs, with 16 models now gaining initial support.
All the above come with dts files for the reference boards. In
addition, these boards are added for the SoCs that are already supported.
- The Milk-V Jupiter board based on SpacemiT K1/M1
- NetCube Systems Kumquat board based on the 32-bit Allwinner V3s SoC
- Three boards based on 32-bit stm32mp1
- 11 distinct board variants from Toradex and one from Variscite,
all based on i.MX6
- Google Pixel Pro 6 phone based on gs101 (Tensor)
- Three additional variants of the i.MX8MP based "Skov" board
- A second variant of the i.MX95 EVK board
- Two boards based on Renesas SoCs
- Four boards based the Rockchip RK35xx series, plus the RK3588
"MNT Reform 2" laptop
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Merge tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There is new support for additional on-chip devices on Apple,
Mediatek, Renesas, Rockchip, Samsung, Google, TI, ST, Nvidia and
Amlogic devices.
The Arm Morello reference platform gets a devicetree for booting in
normal aarch64 mode. The hardware supports experimental CHERI support,
which requires a modified kernel.
The AMD (formerly Xilinx) Versal NET SoC gets added, this is a
combined FPGA with Cortex-A78 CPUs in a SoC.
Six new ST STM32MP2 SoC variants are added. Like the earlier
STM32MP25, the MP211, MP213, MP215, MP231, MP233 and MP235 models are
based on one or two Cortex-A35 cores but each feature a different set
of I/O devices.
Mediatek MT8370 is a minor variation of MT8390 with fewer CPU and GPU
cores
Apple T2 is the baseboard management controller on earlier Intel CPU
based Macs, with 16 models now gaining initial support.
All the above come with dts files for the reference boards. In
addition, these boards are added for the SoCs that are already
supported:
- The Milk-V Jupiter board based on SpacemiT K1/M1
- NetCube Systems Kumquat board based on the 32-bit Allwinner V3s SoC
- Three boards based on 32-bit stm32mp1
- 11 distinct board variants from Toradex and one from Variscite, all
based on i.MX6
- Google Pixel Pro 6 phone based on gs101 (Tensor)
- Three additional variants of the i.MX8MP based "Skov" board
- A second variant of the i.MX95 EVK board
- Two boards based on Renesas SoCs
- Four boards based the Rockchip RK35xx series, plus the RK3588 'MNT
Reform 2' laptop"
* tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (538 commits)
arm64: dts: Add gpio_intc node for Amlogic A5 SoCs
arm64: dts: Add gpio_intc node for Amlogic A4 SoCs
arm64: dts: hi3660: Add property for fixing CPUIdle
arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0
arm64: dts: marvell: Use preferred node names for "simple-bus"
arm64: dts: marvell: Drop unused CP11X_TYPE define
arm64: dts: marvell: Move arch timer and pmu nodes to top-level
arm64: dts: rockchip: Fix PWM pinctrl names
arm64: dts: rockchip: fix RK3576 SCMI clock IDs
dt-bindings: clock: rk3576: add SCMI clocks
arm64: dts: rockchip: Fix pcie reset gpio on Orange Pi 5 Max
arm64: dts: amd/seattle: Drop undocumented "spi-controller" properties
arm64: dts: amd/seattle: Fix bus, mmc, and ethernet node names
arm64: dts: amd/seattle: Move and simplify fixed clocks
arm64: dts: amd/seattle: Base Overdrive B1 on top of B0 version
arm64: dts: rockchip: Enable HDMI audio output for ArmSoM Sige7
arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C
arm64: dts: rockchip: Add SDHCI controller for RK3528
arm64: dts: rockchip: Remove bluetooth node from rock-3a
arm64: dts: rockchip: Move rk356x scmi SHMEM to reserved memory
...
Enabling the GPU power domain requires that the GPU regulator is
enabled. The regulator is enabled at boot time, but gets disabled
automatically when there are no users.
This means the system might run into a failure state hanging the
whole system for the following use cases:
* if the GPU driver is being probed late (e.g. build as a
module and firmware is not in initramfs), the regulator
might already have been disabled. In that case the power
domain is enabled before the regulator.
* unbinding the GPU driver will disable the PM domain and
the regulator. When the driver is bound again, the PM
domain will be enabled before the regulator and error
appears.
Avoid this by adding an explicit regulator dependency to the
power domain.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reported-by: Adrián Martínez Larumbe <adrian.larumbe@collabora.com>
Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
For hdmi0_sound, use the simple-audio-card driver with the hdmi0 QP node
as CODEC and the i2s5 device as CPU.
Similarly for hdmi1_sound, the CODEC is the hdmi1 node and the CPU is
i2s6, but only added in the rk3588-extra.dtsi device tree as the second
TX HDMI port is not available on base versions of the SoC.
The simple-audio-card,mclk-fs value is set to 128 as it is done in
the downstream driver.
The #sound-dai-cells value is set to 0 in the hdmi0 and hdmi1 nodes so
that they can be used as audio codec nodes.
Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger Haikou
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Fixes: 419d191810 ("ASoC: simple-card-utils: use __free(device_node) for device node")
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/20250217215641.372723-3-detlev.casanova@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the RK3588's standalone hardware random number generator node to its
device tree, and enable it.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250204-rk3588-trng-submission-v2-6-608172b6fd91@collabora.com
[changed reset-id to its numeric value while the constant makes its
way through the crypto tree]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Remove Optee node from rk3588 devicetree. When Optee is present and
used the node will be added automatically by U-Boot when
CONFIG_OPTEE_LIB=y and CONFIG_SPL_ATF_NO_PLATFORM_PARAM is not set.
When Optee is not present or used, the node will trigger a probe
that generates a (harmless) message on the kernel log.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20250130181005.6319-1-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The SMMU architecture requires wired interrupts to be edge triggered,
which does not align with the DT description for the RK3588. This leads
to interrupt storms, as the SMMU continues to hold the pin high and only
pulls it down for a short amount when issuing an IRQ. Update the DT
description to be in line with the spec and perceived reality.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Fixes: cd81d3a069 ("arm64: dts: rockchip: add rk3588 pcie and php IOMMUs")
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Link: https://lore.kernel.org/r/Z6pxme2Chmf3d3uK@windev.fritz.box
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP
and eDP Link. Therefore, it is better to name it hdptxphy0 other than
hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com
[added armsom-sige7, where hdmi-support was added recently and also
the hdptxphy0-as-dclk source I just added]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.
For now only HDMI0 output is supported, hence add the related PLL clock.
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Since commit c4b09c5620 ("phy: phy-rockchip-samsung-hdptx: Add clock
provider support"), the HDMI PHY PLL can be used as an alternative and
more accurate pixel clock source for VOP2 to improve display modes
handling on RK3588 SoC.
Add the missing #clock-cells property to allow using the clock provider
functionality of HDMI0 PHY.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The tsadc driver does not handle pinctrl "gpio" and "otpout".
Let's use the correct pinctrl names "default" and "sleep".
Additionally, Alexey Charkov's testing [1] has established that
it is necessary for pinctrl state to reference the &tsadc_shut_org
configuration rather than &tsadc_shut for the driver to function correctly.
[1] https://lkml.org/lkml/2025/1/24/966
Fixes: 32641b8ab1 ("arm64: dts: rockchip: add rk3588 thermal sensor")
Cc: stable@vger.kernel.org
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Link: https://lore.kernel.org/r/20250130053849.4902-1-eagle.alexander923@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The preferred way to denote hardware with non-coherent DMA is to use the
"dma-noncoherent" DT property, at both the GIC redistributor and the GIC ITS
levels, [1] instead of relying on the compatibles to handle hardware errata,
in this case the Rockchip 3588001 errata. [2]
Let's have the preferred way employed in the base Rockchip RK3588 SoC dtsi,
which also goes along with adding initial support for the Rockchip RK3582 SoC
variant, with its separate compatible. [2][3]
[1] Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
[2] https://lore.kernel.org/linux-rockchip/86msgoozqa.wl-maz@kernel.org/
[3] https://lore.kernel.org/linux-rockchip/20241222030355.2246-4-naoki@radxa.com/
Cc: Marc Zyngier <maz@kernel.org>
Cc: FUKAUMI Naoki <naoki@radxa.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/fa1a672dae3644bb3caa58f03216d0ca349db88b.1736279094.git.dsimic@manjaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Commit cd81d3a069 ("arm64: dts: rockchip: add rk3588 pcie and php
IOMMUs") added the rk3588 SoC's pcie IOMMU and php IOMMU as disabled.
The mmu600_pcie is connected with the five PCIe controllers.
See 8.2 Block Diagram, in rk3588 TRM (Technical Reference Manual).
The five PCIe controllers are:
pcie3x4, pcie3x2, pcie2x1l0, pcie2x1l1, pcie2x1l2.
pcie3x4 can run in either Root Complex mode or Endpoint mode, the other
four PCIe controllers can only run in Root Complex mode. To describe this
we thus have six different device nodes in the device tree.
A PCIe controller in Root Complex mode needs to specify an iommu-map, such
that the device knows how to convert a Requester ID (PCI BDF) to an IOMMU
master ID (stream ID). (A PCIe controller in Endpoint mode should use the
iommus property, just like a regular device.)
If you look at the device tree bindings for msi-map and iommu-map, you can
see that the conversion from Requester ID to MSI-specifier data is the same
as the conversion from Requester ID to IOMMU specifier data. Thus it is
sensible to define the iommu-map property value similar to the msi-map,
such that the conversion will be identical.
Add the proper iommu device tree properties for these six device nodes
connected to the mmu600_pcie, so that we can enable the mmu600_pcie IOMMU.
(The mmu600_php IOMMU is not touched, so it is still disabled.)
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Link: https://lore.kernel.org/r/20241107123732.1160063-2-cassel@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This release adds the devicetree files for an impressive number of new
SoC variants, though as expected these are all related to others we
already support:
- The microchip sam9x7 devicetree is now added, after the device driver
and platform code has already made it in. This is likely the last ARMv5
(!) platform to ever get added, updating the 20+ year old at91/sam9
platform wtih DDR3 memory and gigabit ethernet.
- On the Apple platform, there are now devicetree files for a number of
A-series SoCs in addition to the M-series ones, these are used
primarily in phones and tablets, but are closely related to the
already supported chips.
- Samsung Exynos 8895 and Exynos 990 are more phone SoCs used in older
Samsung Galaxy phones.
- Qualcomm Snapdragon 778G (SM7325) is another phone SoC, closely related
to the Snapdragon 7c+ Gen 3 (SC7280) used in low-end laptops.
- Rockchip RK3528 and RK3576 are new variants of their TV box and Tablet
chips, still using the older ARMv8.0 cores from RK3328/RK3399 but
with a newer process and other improvements from the RK35xx (otherwise
ARMv8.2) chips. RK3566T and RK3399-S are also added, these are just
lower-cost versions of their normal counterparts.
- TI J742S2 is a feature-reduced version of the J784s4
industrial/automotive SoC, with fewer CPU cores.
- Sophgo SG2002 is an embedded SoC with one RISC-V (C906) and one ARM
(Cortex-A53) core, at this point support is only added for running
on the RISC-V side on the LicheeRV Nano board.
A total of 92 new .dts files describing individual machines is added,
which must be a new record. The majority of these is for the newly added
chips above, notably all the Apple phones and tablets. The other new
machines include nine industrial/embedded boards with NXP i.MX6 or i.MX8
SoCs, eight for Rockchips RK35XX and one or two each for Rockchips RV1109,
RK3308, Allwinner A33, Tegra 234, Qualcomm qcs9100/sc8280xp/x1e80100,
TI AM625 and Starfive JH7110.
As usual there are also many newlyad added features in existing boards
as well as cleanups and minor bugfixes.
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Merge tag 'soc-dt-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"This release adds the devicetree files for an impressive number of new
SoC variants, though as expected these are all related to others we
already support:
- The microchip sam9x7 devicetree is now added, after the device
driver and platform code has already made it in. This is likely the
last ARMv5 (!) platform to ever get added, updating the 20+ year
old at91/sam9 platform with DDR3 memory and gigabit ethernet.
- On the Apple platform, there are now devicetree files for a number
of A-series SoCs in addition to the M-series ones, these are used
primarily in phones and tablets, but are closely related to the
already supported chips.
- Samsung Exynos 8895 and Exynos 990 are more phone SoCs used in
older Samsung Galaxy phones.
- Qualcomm Snapdragon 778G (SM7325) is another phone SoC, closely
related to the Snapdragon 7c+ Gen 3 (SC7280) used in low-end
laptops.
- Rockchip RK3528 and RK3576 are new variants of their TV box and
Tablet chips, still using the older ARMv8.0 cores from
RK3328/RK3399 but with a newer process and other improvements from
the RK35xx (otherwise ARMv8.2) chips. RK3566T and RK3399-S are also
added, these are just lower-cost versions of their normal
counterparts.
- TI J742S2 is a feature-reduced version of the J784s4
industrial/automotive SoC, with fewer CPU cores.
- Sophgo SG2002 is an embedded SoC with one RISC-V (C906) and one ARM
(Cortex-A53) core, at this point support is only added for running
on the RISC-V side on the LicheeRV Nano board.
A total of 92 new .dts files describing individual machines is added,
which must be a new record. The majority of these is for the newly
added chips above, notably all the Apple phones and tablets. The other
new machines include nine industrial/embedded boards with NXP i.MX6 or
i.MX8 SoCs, eight for Rockchips RK35XX and one or two each for
Rockchips RV1109, RK3308, Allwinner A33, Tegra 234, Qualcomm
qcs9100/sc8280xp/x1e80100, TI AM625 and Starfive JH7110.
As usual there are also many newly added features in existing boards
as well as cleanups and minor bugfixes"
* tag 'soc-dt-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (718 commits)
arm64: dts: apm: Remove unused and undocumented "bus_num" property
arm: dts: spear13xx: Remove unused and undocumented "pl022,slave-tx-disable" property
arm64: dts: amd: Remove unused and undocumented "amd,zlib-support" property
arm64: dts: lg131x: Update spi clock properties
arm64: dts: seattle: Update spi clock properties
arm64: dts: rockchip: use less broad pinctrl for pcie3x1 on Radxa E25
arm64: dts: rockchip: add Radxa ROCK 5C
dt-bindings: arm: rockchip: add Radxa ROCK 5C
arm64: dts: rockchip: orangepi-5-plus: Enable GPU
arm64: dts: rockchip: enable USB3 on NanoPC-T6
arm64: dts: rockchip: adapt regulator nodenames to preferred form
arm64: dts: rockchip: Enable HDMI display for rk3588 Cool Pi GenBook
arm64: dts: rockchip: Enable HDMI display for rk3588 Cool Pi 4B
arm64: dts: rockchip: Enable HDMI0 for rk3588 Cool Pi CM5 EVB
arm64: dts: rockchip: Enable HDMI on NanoPi R6C/R6S
arm64: dts: rockchip: Enable GPU on NanoPi R6C/R6S
arm64: dts: rockchip: Enable HDMI on Hardkernel ODROID-M2
arm64: dts: rockchip: Remove non-removable flag from sdmmc on rk3576-sige5
arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node
arm64: dts: allwinner: pinephone: Add mount matrix to accelerometer
...
Move the "l3_cache" node outside the "cpus" node in the base dtsi file for
Rockchip RK3588(S) SoCs. The A55 and A76 CPU cores in these SoCs belong to
the ARM DynamIQ IP core lineup, which places the L3 cache outside the CPUs
and into the DynamIQ Shared Unit (DSU). [1] Thus, moving the L3 cache DT
node one level higher in the DT improves the way the physical topology of
the RK3588(S) SoCs is represented in the SoC dtsi files.
While there, add a comment that explains it briefly, to save curious readers
from the need to reference the repository log for a clarification.
[1] ARM DynamIQ Shared Unit revision r4p0 TRM, version 0400-02
Fixes: c9211fa260 ("arm64: dts: rockchip: Add base DT for rk3588 SoC")
Helped-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/84264d0713fb51ae2b9b731e28fc14681beea853.1727345965.git.dsimic@manjaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
New SoC support for Broadcom bcm2712 (Raspberry Pi 5) and Renesas
R9A09G057 (RZ/V2H(P)) and Qualcomm Snapdragon 414 (MSM8929), all three
of these are variants of already supported chips, in particular the last
one is almost identical to MSM8939.
Lots of updates to Mediatek, ASpeed, Rockchips, Amlogic, Qualcomm,
STM32, NXP i.MX, Sophgo, TI K3, Renesas, Microchip at91, NVIDIA Tegra,
and T-HEAD.
The added Qualcomm platform support once again dominates the changes,
with seven phones and three laptops getting added in addition to
many new features on existing machines. The Snapdragon X1E support
specifically keeps improving.
The other new machines are:
- eight new machines using various 64-bit Rockchips SoCs, both
on the consumer/gaming side and developer boards
- three industrial boards with 64-bit i.MX, which is a very
low number for them.
- four more servers using a 32-bit Speed BMC
- three boards using STM32MP1 SoCs
- one new machine each using allwinner, amlogic, broadcom
and renesas chips.
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Merge tag 'soc-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"New SoC support for Broadcom bcm2712 (Raspberry Pi 5) and Renesas
R9A09G057 (RZ/V2H(P)) and Qualcomm Snapdragon 414 (MSM8929), all three
of these are variants of already supported chips, in particular the
last one is almost identical to MSM8939.
Lots of updates to Mediatek, ASpeed, Rockchips, Amlogic, Qualcomm,
STM32, NXP i.MX, Sophgo, TI K3, Renesas, Microchip at91, NVIDIA Tegra,
and T-HEAD.
The added Qualcomm platform support once again dominates the changes,
with seven phones and three laptops getting added in addition to many
new features on existing machines. The Snapdragon X1E support
specifically keeps improving.
The other new machines are:
- eight new machines using various 64-bit Rockchips SoCs, both on the
consumer/gaming side and developer boards
- three industrial boards with 64-bit i.MX, which is a very low
number for them.
- four more servers using a 32-bit Speed BMC
- three boards using STM32MP1 SoCs
- one new machine each using allwinner, amlogic, broadcom and renesas
chips"
* tag 'soc-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (672 commits)
arm64: dts: allwinner: h5: NanoPi NEO Plus2: Use regulators for pio
arm64: dts: mediatek: add audio support for mt8365-evk
arm64: dts: mediatek: add afe support for mt8365 SoC
arm64: dts: mediatek: mt8186-corsola: Disable DPI display interface
arm64: dts: mediatek: mt8186: Add svs node
arm64: dts: mediatek: mt8186: Add power domain for DPI
arm64: dts: mediatek: mt8195: Correct clock order for dp_intf*
arm64: dts: mt8183: add dpi node to mt8183
arm64: dts: allwinner: h5: NanoPi Neo Plus2: Fix regulators
arm64: dts: rockchip: add CAN0 and CAN1 interfaces to mecsbc board
arm64: dts: rockchip: add CAN-FD controller nodes to rk3568
arm64: dts: nuvoton: ma35d1: Add uart pinctrl settings
arm64: dts: nuvoton: ma35d1: Add pinctrl and gpio nodes
arm64: dts: nuvoton: Add syscon to the system-management node
ARM: dts: Fix undocumented LM75 compatible nodes
arm64: dts: toshiba: Fix pl011 and pl022 clocks
ARM: dts: stm32: Use SAI to generate bit and frame clock on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: Switch bitclock/frame-master to flag on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: Sort properties in audio endpoints on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: Add MECIO1 and MECT1S board variants
...
RK3588 VO0 and VO1 GRFs are not identical (though quite similar in terms
of layout) and, therefore, incorrectly shared the compatible string.
Since the related binding document has been updated to use dedicated
strings, update the compatibles for vo{0,1}_grf DT nodes accordingly.
Additionally, for consistency, set the full region size (16KB) for
VO1_GRF.
Reported-by: Conor Dooley <conor@kernel.org>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240828-rk3588-vo-grf-compat-v2-2-4db2f791593f@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP,
but can be used as a cluster (i.e. sharing work between the cores).
These cores are called VEPU121 in the TRM. The TRM describes one more
VEPU121, but that is combined with a Hantro H1. That one will be handled
using the VPU binding instead.
Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20240827181206.147617-2-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
RK3588j uses a different set of OPPs for its GPU, both in terms of
allowed frequencies and in terms of voltages.
Move the GPU OPPs table into per-variant .dtsi files to accommodate
for this difference.
The table for RK3588j is adapted from Rockchip downstream sources [1],
while RK3588 one is moved verbatim into the per-variant .dtsi file.
The values provided for RK3588 in the downstream sources match those
in the original commit.
[1] 604cec4004/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
Fixes: 6fca4edb93 ("arm64: dts: rockchip: Add rk3588 GPU node")
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-8-c1f5f3267f1e@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
As the GPU support on RK3588 has been merged upstream, along with OPP
values, add a corresponding cooling map for passive cooling using the GPU.
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-3-c1f5f3267f1e@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This includes the necessary device tree data to allow thermal
monitoring on RK3588(s) using the on-chip TSADC device, along with
trip points for automatic thermal management.
Each of the CPU clusters (one for the little cores and two for
the big cores) get a passive cooling trip point at 85C, which
will trigger DVFS throttling of the respective cluster upon
reaching a high temperature condition.
All zones also have a critical trip point at 115C, which will
trigger a reset.
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-1-c1f5f3267f1e@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Rename the Rockchip RK3588 SoC dtsi files and, consequently, adjust their
contents appropriately, to prepare them for the ability to specify different
CPU and GPU OPPs for each of the supported RK3588 SoC variants.
As already discussed, [1][2][3][4] some of the RK3588 SoC variants require
different OPPs, and it makes more sense to have the OPPs already defined when
a board dts(i) file includes one of the SoC variant dtsi files (rk3588.dtsi,
rk3588j.dtsi or rk3588s.dtsi), rather than requiring the board dts(i) file
to also include a separate rk3588*-opp.dtsi file. The choice of the SoC
variant is already made by the inclusion of the SoC dtsi file into the board
dts(i) file, and it doesn't make much sense to, effectively, allow the board
dts(i) file to include and use an incompatible set of OPPs for the already
selected RK3588 SoC variant.
The new naming scheme for the RK3588 SoC dtsi files uses "-base" and "-extra"
suffixes to denote the DT data shared between all RK5588 SoC variants, and
the DT data shared between the unrestricted SoC variants, respectively.
For example, the DT data for the RK3588 includes both rk3588-base.dtsi and
rk3588-extra.dtsi, because it's an unrestricted SoC variant, while the DT
data for the RK3588S variant includes rk3588-base.dtsi only, because it's
a restricted SoC variant, feature- and interface-wise. This achieves a more
logical naming of the RK3588 SoC dtsi files, which reflects the way DT data
for the SoC variants is built by "stacking" the SoC variant features made
available through the "-base" and "-extra" SoC dtsi files. Additionally,
the SoC variant dtsi files (rk3588.dtsi, rk3588j.dtsi and rk3588s.dtsi) are
no longer parents to any other SoC variant dtsi files, which should help with
making the new "stacking" approach cleaner and easier to follow.
The RK3588 pinctrl dtsi files are also renamed in the same way, for the sake
of consistency. This also keeps the "-base" and "-extra" groups of the dtsi
files together when looked at in a directory listing, which is helpful.
The per-SoC-variant OPPs should go directly into the SoC dtsi files, if no
more than one SoC variant uses those OPPs, or be put into a separate "-opp"
dtsi file that's shared between and included from two or more SoC variant
dtsi files. An example for the former is the non-shared OPP data that should
go directly into the RK3588J SoC variant dtsi file (i.e. rk3588j.dtsi), and
an example for the latter is the shared OPP data that should be put into
rk3588-opp.dtsi and be included from the RK3588 and RK3588S SoC variant dtsi
files (i.e. rk3588.dtsi and rk3588s.dtsi, respectively). Consequently, if
the OPPs for the RK3588 and RK3588S SoC variants are ever made different,
the shared rk3588-opp.dtsi file should be deleted and the new OPPs should
be put directly into rk3588.dtsi and rk3588s.dtsi. [4]
No functional changes are introduced, which was validated by decompiling and
comparing all affected dtb files before and after these changes.
As a side note, due to the nature of introduced changes, this commit is best
viewed using the --break-rewrites option for git-log(1).
[1] https://lore.kernel.org/linux-rockchip/646a33e0-5c1b-471c-8183-2c0df40ea51a@cherry.de/
[2] https://lore.kernel.org/linux-rockchip/CABjd4Yxi=+3gkNnH3BysUzzYsji-=-yROtzEc8jM_g0roKB0-w@mail.gmail.com/
[3] https://lore.kernel.org/linux-rockchip/035a274be262528012173d463e25b55f@manjaro.org/
[4] https://lore.kernel.org/linux-rockchip/673dcf47596e7bc8ba065034e339bb1bbf9cdcb0.1716948159.git.dsimic@manjaro.org/T/#u
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/9ffedc0e2ca7f167d9d795b2a8f43cb9f56a653b.1717923308.git.dsimic@manjaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
