3 Commits

Author	SHA1	Message	Date
Michael Riesch	381b6d432f	arm64: dts: rockchip: add pinctrls for 16-bit/18-bit rgb interface to rk356x ... The rk3568-pinctrl.dtsi only defines the 24-bit RGB interface. Add separate nodes for the 16-bit and 18-bit version, respectively. While at it, split off the clock/sync signals from the data signals. The exact mapping of the data pins was discussed here: https://lore.kernel.org/linux-rockchip/f33a0488-528c-99de-3279-3c0346a03fd6@wolfvision.net/T/ Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20230124054706.3921383-7-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2023-01-29 13:05:16 +01:00
Peter Geis	1330875dc2	arm64: dts: rockchip: add rk3568 tsadc nodes ... Add the thermal and tsadc nodes to the rk3568 device tree. There are two sensors, one for the cpu, one for the gpu. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210728180034.717953-6-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2021-09-15 17:50:40 +02:00
Liang Chen	a3adc0b907	arm64: dts: rockchip: add core dtsi for RK3568 SoC ... RK3568 is a high-performance and low power quad-core application processor designed for personal mobile internet device and AIoT equipment. This patch add basic core dtsi file for it. We use scmi_clk for cortex-a55 instead of standard ARMCLK, so that kernel/uboot/rtos can change cpu clk with the same code in ATF, and we will enalbe a special high-performance PLL when high frequency is required. The smci_clk code is in ATF, and clkid for cpu is 0, as below: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x0>; clocks = <&scmi_clk 0>; }; Signed-off-by: Liang Chen <cl@rock-chips.com> Link: https://lore.kernel.org/r/20210622020517.13100-4-cl@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2021-06-22 12:21:55 +02:00