bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to describe various node usage during
boot phases with DT. Add bootph-all for all nodes that are used in the
bootloader on Renesas R-Car SoCs.
All SoC require CPG clock and its input clock, RST Reset, PFC pin
control and PRR ID register access during all stages of the boot
process, those are marked using bootph-all property, and so is the SoC
bus node which contains these IP.
Each board console UART is also marked as bootph-all to make it
available in all stages of the boot process.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250209180616.160253-2-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The Renesas Ethernet Switch has three independent ports. Each port can
act as a separate interface, and can be enabled or disabled
independently. Currently all ports are enabled by default, hence board
DTS files that enable the switch must disable all unused ports
explicitly.
Disable all ports by default, and explicitly enable ports that are used,
next to their configuration.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://lore.kernel.org/c4688de8e3289ad82c2cd85f0893eac660ac8890.1737649969.git.geert+renesas@glider.be
Introduce labels for each rswitch port in the form 'rswitch_portN'.
Those can be used to access rswitch port nodes directly, which is going
to be useful in reducing DT indentation slightly as well as in the DT
/aliases node to reference the rswitch ports as ethernetN interfaces.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250118111344.361617-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Since IMSSTR register was undocumented on the latest datasheet and
dt-bindings of renesas,ipmmu-vmsa was updated about
the renesas,ipmmu-main property, revise the property on each cache
IPMMU node.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20230123013448.1250991-2-yoshihiro.shimoda.uh@renesas.com
[geert: Drop indices from renesas,ipmmu-main properties]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The documentation provides information about the placement of the zones,
so that can be used for more descriptive labels.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230209200735.3882-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The GICv3 interrupts binding does not have a cpumask. The CPU mask only
applies to pre-GICv3. So just drop using them from GICv3 systems.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230206002136.29401-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add operating points for running the Cortex-A55 CPU cores on R-Car S4-8
at various speeds, up to the maximum supported frequency (1200 MHz).
R-Car S4-8 has 8 Cortex-A55 cores, grouped in 4 clusters.
CA55 Sub-System 0 (first 2 clusters / CPU cores 0-3) is clocked by Z0φ.
CA55 Sub-System 1 (last 2 clusters / CPU cores 4-7) is clocked by Z1φ.
As the two sets of clusters are driven by separate clocks, this requires
specifying two separate tables (using the same operating performance
point values), with "opp-shared" to indicate that the CPU cores in each
set share state.
Based on a patch in the BSP by Tho Vu.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Link: https://lore.kernel.org/r/ae78351d702a53702a1d5fa26675fe982b99cdf5.1669817508.git.geert+renesas@glider.be
As serial communication requires a clean clock signal, the Serial
Communication Interfaces with FIFO (SCIF) are clocked by a clock that is
not affected by Spread Spectrum or Fractional Multiplication.
Hence change the clock input for the SCIF Baud Rate Generator internal
clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81.
Fixes: c62331e822 ("arm64: dts: renesas: Add Renesas R8A779F0 SoC support")
Fixes: 4075314425 ("arm64: dts: renesas: r8a779f0: Add SCIF nodes")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221103143440.46449-5-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
As serial communication requires a clean clock signal, the High Speed
Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock
that is not affected by Spread Spectrum or Fractional Multiplication.
Hence change the clock input for the HSCIF Baud Rate Generator internal
clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81.
Fixes: 01a787f78b ("arm64: dts: renesas: r8a779f0: Add HSCIF nodes")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221103143440.46449-4-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Extracted from a bigger patch in the BSP, rebased, reg length corrected,
and DMA properties added.
Signed-off-by: Linh Phung <linh.phung.jy@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220614095242.8264-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Extracted from a bigger patch in the BSP, rebased and DMA
properties added.
Signed-off-by: Linh Phung <linh.phung.jy@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220614095109.8175-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Describe the clocks for the eight Cortex-A55 CPU cores.
CA55 Sub-System 0 (first 2 clusters / CPU cores 0-3) is clocked by Z0φ.
CA55 Sub-System 1 (last 2 clusters / CPU cores 4-7) is clocked by Z1φ.
For now no operating points are defined.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/c502087f9affa86dd665def0d990d277a51cc75c.1654701480.git.geert+renesas@glider.be
Complete the description of the Cortex-A55 CPU cores and L3 cache
controllers on the Renesas R-Car S4-8 (R8A779F0) SoC, including CPU
topology and PSCI support for enabling CPU cores.
R-Car S4-8 has 8 Cortex-A55 cores, grouped in 4 clusters.
Based on patches in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/d6af5975090d5830cb053b52400439bd1cbe8fc7.1654701480.git.geert+renesas@glider.be
Describe the cache configuration for the first Cortex-A55 CPU core on
the Renesas R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/a63715ce1d2d2fcc7ab987f7a1b40847965e8d6a.1654701480.git.geert+renesas@glider.be
Add support for 3 TSC nodes of thermal. The 4th node is for the control
domain and not for Linux.
Signed-off-by: Linh Phung <linh.phung.jy@renesas.com>
[wsa: rebased, fixed resource size, removed unused 4th node breaking probe]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220525151355.24175-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add a device node for the Pin Function Controller on the Renesas R-Car
S4-8 (R8A779F0) SoC.
Note that the register block does not include registers for banks 4-7,
as they can only be accessed from the Control Domain.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/cf4d261ba1253879e117f1598b9f47798cbda635.1645458249.git.geert+renesas@glider.be
Add a device node for the RCLK Watchdog Timer (RWDT) on the Renesas
R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/556a7f41bdadceecbe8b59b79ac7e9f592ca17a2.1642525158.git.geert+renesas@glider.be
