The interconnect property is already present in the qce node, which
is the consumer of the cryptobam, so no need for an interconnect property
as documented by the bindings.
Fixes: 433477c3bf ("arm64: dts: qcom: sm8550: add QCrypto nodes")
Suggested-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230209-topic-sm8550-upstream-cryptobam-remove-interconnect-v1-1-84587c7bad0f@linaro.org
The proper name for it is power-management. Currently, with the node
name being power-controller, the bindings check fails due to the
property #power-domain-cells missing.
Fixes: ffc50b2d38 ("arm64: dts: qcom: Add base SM8550 dtsi")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230127131441.1157679-1-abel.vesa@linaro.org
Generic SMMU compatibles are not allowed alone and we expect specific
one.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230127115513.268843-1-krzysztof.kozlowski@linaro.org
The serial/UART device node does not have children with unit addresses,
so address/size cells are not correct.
Fixes: 377972ac74 ("arm64: dts: qcom: sm8550: add I2C Master Hub nodes")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230124084951.38195-4-krzysztof.kozlowski@linaro.org
The USB-DP PHY resets have been switched.
Fixes: 7f7e5c1b03 ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230123101607.2413-1-johan+linaro@kernel.org
Add the ADSP GPR (Generic Packet Router) and LPASS LPI (Low Power Audio
SubSystem Low Power Island) pin controller nodes used as part of audio
subsystem on SM8550.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Shortened stream mask, per Konrad's request]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230206150744.513967-1-krzysztof.kozlowski@linaro.org
This adds support for the aDSP, cDSP and MPSS Subsystems found in
the SM8550 SoC.
The aDSP, cDSP and MPSS needs:
- smp2p nodes to get event back from the subsystems
- remoteproc nodes with glink-edge subnodes providing all needed
resources to start and run the subsystems
In addition, the MPSS Subsystem needs a rmtfs_mem dedicated
memory zone.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-remoteproc-v3-2-815a1753de34@linaro.org
Add devices tree nodes describing display hardware on SM8550:
- Display Clock Controller
- MDSS
- MDP
- two DSI controllers and DSI PHYs
This does not provide support for DP controllers present on the SM8550.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104-topic-sm8550-upstream-dts-display-v4-1-1729cfc0e5db@linaro.org
Currently, available frequencies for all CPUs are appearing as 2x
of the actual frequencies. Use xo clock source as bi_tcxo in the
cpufreq-hw node to fix this.
Signed-off-by: Pavankumar Kondeti <quic_pkondeti@quicinc.com>
Tested-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230117093533.3710000-1-quic_pkondeti@quicinc.com
Add base dtsi for SM8550 SoC and includes base description of
CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved
memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq,
interconnect, thermal sensor, cpu cooling maps and SMMU nodes
which helps boot to shell with console on boards with this SoC.
Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-3-abel.vesa@linaro.org
