In order to support multiple revisions of the sa8775p-ride board, create
a .dtsi containing the common parts and split out the ethernet bits into
the actual board file as they will change in revision 3.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20240627114212.25400-3-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The volume down key is controlled by PMIC via the PON hardware on
sa8775p platform, so enable the same for sa8775p-ride.
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Link: https://lore.kernel.org/r/20231107120503.28917-1-quic_shazhuss@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
There's an irq hooked up, so let's describe it.
Prior to commit 9757300d27
("pinctrl: qcom: Add intr_target_width field to support increased number of interrupt targets")
one would not see the IRQ fire, despite some (invasive) debugging
showing that the GPIO was in fact asserted, resulting in the interface
staying down.
Now that the IRQ is properly routed we can describe it.
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230817213815.638189-3-ahalaney@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
There's an irq hooked up, so let's describe it.
Prior to commit 9757300d27
("pinctrl: qcom: Add intr_target_width field to support increased number of interrupt targets")
one would not see the IRQ fire, despite some (invasive) debugging
showing that the GPIO was in fact asserted, resulting in the interface
staying down.
Now that the IRQ is properly routed we can describe it.
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230817213815.638189-2-ahalaney@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
These are the devicetree updates for Arm and RISC-V based SoCs,
mainly from Qualcomm, NXP/Freescale, Aspeed, TI, Rockchips,
Samsung, ST and Starfive.
Only a few new SoC got added:
- TI AM62P5, a variant of the existing Sitara AM62x family
- Intel Agilex5, an FPGFA platform that includes an
Cortex-A76/A55 SoC.
- Qualcomm ipq5018 is used in wireless access points
- Qualcomm SM4450 (Snapdragon 4 Gen 2) is a new low-end mobile
phone platform.
In total, 29 machines get added, which is low because of the summer
break. These cover SoCs from Aspeed, Broadcom, NXP, Samsung, ST,
Allwinner, Amlogic, Intel, Qualcomm, Rockchip, TI and T-Head. Most of
these are development and reference boards.
Despite not adding a lot of new machines, there are over 700 patches in
total, most of which are cleanups and minor fixes.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTuZOQACgkQYKtH/8kJ
UieJGw/5AWNde1VYY/3uhdHSNeXtF+1LICZYoLQiSTWbpnlEoLhQseymRCybWRhd
882TLCuEMrHV+ftP5z+kdYS+QJE3K8GNRxp4vAgLTRwnZItEE3qD8/jNeTtK5BqT
7h9OYZJQhfczsIXISIljsvez2T3n5fA1glq2drc2fLl9AbEYvlByDCtCNmzqMYli
II/S03vJqT3eFnOwut70EdFtnW3FIJ+HJLWu46zWLhrx2XJVS8hNaWqhQ3uKZ58p
Q9cWAltu4biaILVpD/0vZST+m77HqcrPtVSwR9uHvzEzDEzYk/GYzn7DDlWgdVbt
DJMkgK1pLJq67KpsefMqgTioCh2FBiWfNQ6FjsgJ06ykXgThLJfbzeeB4zU4fnDT
YmcV/8gR6Np/wNeSBlPNLI6BZ1EF4h0Lkm6p//QgayYhdMVbE59K+SNwq4wps24l
JU3dcxxblwpVmAaKSL5p0lbYTn8VKuz9rcXYIziQm1m8zaCwjq863bDFJKz8JsP8
0tQ/azvS4Off9fKIMbUE4fiFmDGhgLTi0XL+GIlOFJF6JS6ToD2nL4FGRBJZPWNn
iPNEV0F/dDnonB7Jfu92NodULY6B0mXs5/q+dPwde6oSpIDU2ORyNRb6Zk4fGC0l
C+iPdb3BErf+GQYBLnRqQaMuV0sA6mN89lC6KlzWwwHK0UUoohg=
=bO3j
-----END PGP SIGNATURE-----
Merge tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM devicetree updates from Arnd Bergmann:
"These are the devicetree updates for Arm and RISC-V based SoCs, mainly
from Qualcomm, NXP/Freescale, Aspeed, TI, Rockchips, Samsung, ST and
Starfive.
Only a few new SoC got added:
- TI AM62P5, a variant of the existing Sitara AM62x family
- Intel Agilex5, an FPGFA platform that includes an Cortex-A76/A55
SoC.
- Qualcomm ipq5018 is used in wireless access points
- Qualcomm SM4450 (Snapdragon 4 Gen 2) is a new low-end mobile phone
platform.
In total, 29 machines get added, which is low because of the summer
break. These cover SoCs from Aspeed, Broadcom, NXP, Samsung, ST,
Allwinner, Amlogic, Intel, Qualcomm, Rockchip, TI and T-Head. Most of
these are development and reference boards.
Despite not adding a lot of new machines, there are over 700 patches
in total, most of which are cleanups and minor fixes"
* tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (735 commits)
arm64: dts: use capital "OR" for multiple licenses in SPDX
ARM: dts: use capital "OR" for multiple licenses in SPDX
arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved
ARM: dts: qcom: apq8064: add support to gsbi4 uart
riscv: dts: change TH1520 files to dual license
riscv: dts: thead: add BeagleV Ahead board device tree
dt-bindings: riscv: Add BeagleV Ahead board compatibles
ARM: dts: stm32: add SCMI PMIC regulators on stm32mp135f-dk board
ARM: dts: stm32: STM32MP13x SoC exposes SCMI regulators
dt-bindings: rcc: stm32: add STM32MP13 SCMI regulators IDs
ARM: dts: stm32: support display on stm32f746-disco board
ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f746-disco
ARM: dts: stm32: add pin map for LTDC on stm32f7
ARM: dts: stm32: add ltdc support on stm32f746 MCU
arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sdm670: Add PDC
riscv: dts: starfive: fix jh7110 qspi sort order
...
Enable the second MAC on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-10-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Once we add a second ethernet node, the MDIO bus names will conflict
unless we provide aliases. Add one for the existing ethernet node.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-9-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
For improved readability order the aliases alphabetically for
sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-8-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add a second SGMII PHY that will be used by EMAC1 on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-7-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
We'll be adding a second SGMII PHY on the same MDIO bus, so let's index
the first one for better readability.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-6-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Device-tree bindings for MDIO define per-PHY reset-gpios as well as a
global reset-gpios property at the MDIO node level which controls all
devices on the bus. The latter is most likely a workaround for the
chicken-and-egg problem where we cannot read the ID of the PHY before
bringing it out of reset but we cannot bring it out of reset until we've
read its ID.
I have proposed a comprehensive solution for this problem in 2020 but it
never got upstream. We do however have workaround in place which allows
us to hard-code the PHY id in the compatible property, thus skipping the
ID scanning.
Let's make the device-tree for sa8775p-ride slightly more correct by
moving the reset-gpios property to the PHY node with its ID put into the
PHY node's compatible.
Link: https://lore.kernel.org/all/20200622093744.13685-1-brgl@bgdev.pl/
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-5-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable the second SerDes PHY on sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-4-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
L4c is the supply for UFS vccq, As per UFS spec range of vccq is
1.14V to 1.26V, There are stability issues when operating at
marginal voltage. Hence configure the min and max vccq voltages
to 1.2V.
Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230711105915.30581-1-quic_narepall@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable the first 1Gb ethernet port on sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230622120142.218055-6-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the MDC and MDIO pin functions for ethernet0 on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230622120142.218055-5-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable the UFS and its PHY on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230411130446.401440-6-brgl@bgdev.pl
Set line names for GPIO lines exposed by PMICs on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-16-brgl@bgdev.pl
Add a new .dtsi file for sa8775p PMICs and add the four PMICs interfaced
to the SoC via SPMI. Enable the PMICs for sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-8-brgl@bgdev.pl
Enable the high-speed UART port connected to the Bluetooth controller on
the sa8775p-adp development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-10-brgl@bgdev.pl
Enable the high-speed UART port connected to the GNSS controller on the
sa8775p-adp development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-9-brgl@bgdev.pl
Enable the SPI interface exposed on the sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-7-brgl@bgdev.pl
This enables the I2C interface on the sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-5-brgl@bgdev.pl
Enable the second instance of the QUPv3 engine on the sa8775p-ride board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-3-brgl@bgdev.pl
This adds basic support for the Qualcomm sa8775p platform and the
reference board: sa8775p-ride. The dt files describe the basics of the
SoC and enable booting to shell.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230214092713.211054-3-brgl@bgdev.pl
