DTS coding style expects labels to be lowercase. No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
For Gen-1 targets like IPQ8074, it is seen that stressing out the
controller in host mode results in HC died error:
xhci-hcd.12.auto: xHCI host not responding to stop endpoint command
xhci-hcd.12.auto: xHCI host controller not responding, assume dead
xhci-hcd.12.auto: HC died; cleaning up
And at this instant only restarting the host mode fixes it. Disable
SuperSpeed instance in park mode for IPQ8074 to mitigate this issue.
Cc: stable@vger.kernel.org
Fixes: 5e09bc51d0 ("arm64: dts: ipq8074: enable USB support")
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240704152848.3380602-3-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Device nodes should have generic names. Use 'clock-controller@' as a GCC
node name instead of a non-generic 'gcc@'.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-14-69c63d0ae1e7@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-15-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
gpio16 will only be used for LCD support, as its NAND/LCDC data[8]
so its bit 9 of the parallel QPIC interface, and ONFI NAND is only 8
or 16-bit with only 8-bit one being supported in our case so that pin
is unused.
It should be dropped from the default NAND pinctrl configuration
as its unused and only needed for LCD.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20240313102713.1727458-1-frut3k7@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add node to support the QUP UART6 controller inside of IPQ8074.
Used by some routers to communicate with a Bluetooth controller.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Link: https://lore.kernel.org/r/20240229205426.232205-1-frut3k7@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Four variants of Samsung Galaxy Core Prime and Grand Prime, built on
MSM8916, and the Hardware Development Kit (HDK) for SM8550, are
introduced.
On X Elite audio and compute remoteprocs, IPCC, PCIe, AOSS QMP, SMP2P,
TCSR, USB, display, audio, and soundwire support is introduced, and
enabled across the CRD and QCP devices.
For SM8650 PCIe controllers are moved to GIC-ITS and msi-map-mask is
defined. Missing qlink-logging reserved-memory region is added for the
modem remoteproc. FastRPC compute contexts are marked dma-coherent.
Audio, USB Type-C and PM8010 support is introduced across MTP and QRD
devices.
GPU cooling devices are hooked up across MSM8916, MSM8939, SC8180X,
SDM630, SDM845, SM6115, SM8150, SM8250, SM8350, and SM8550.
UFS PHY clocks are corrected across MSM8996, MSM8998, SC8180X, SC8280XP,
SDM845, SM6115, SM6125, SM8150, SM8250, SM8350, SM8550, and SM8650.
PCI MSI interrupts are wired up across SM8150, SM8250, SM8350, SM8450,
SM8550, SM8650, SC7280, and SC8180X
On IPQ6018 QUP5 I2C, tsens sand thermal zones are defined. The Inline
Crypto Engine (ICE) is enabled for IPQ9574.
On MSM8953 the GPU and its IOMMU is introduced, the reset for the
display subsystem is also wired up.
VLS CLAMP registers are specified for USB3 PHYs on MSM8998, QCM2290, and
SM6115.
USB Type-C port management is enabled on QRB4210 RB2.
On the SA8295P ADP the MAX20411 regulator powering the GPU rails is
introduced and the GPU is enabled. The first PCI instance on SA8540P
Ride is disabled for now, as a fix for the interrupt storm produced here
has not been presented.
On SA8775P the firmware memory map has changed and is updated. Safety
IRQ is added to the Ethernet controller.
On SC7180 UFS support is introduced and the cros-ec-spi is marked as
wakeup source.
For SC7280 capacity and DPC properties are added, cryptobam definition
is improved to work in more firmware environments, more Chrome-specific
properties are moved out from main dtsi, and cros-ec-spi is maked as a
wakeup source. Slimbus definition is added to the platform.
A missing reserved-memory range is added to Fairphone FP5, PMIC GLINK
and Venus are enabled. LEDs are introduced and voltage settings
corrected on the QCM6490 IDP, and RB3gen2 sees the same voltage changes
and GCC protected clocks are introduced to make the board boot properly.
RPMh sleep stats and a variety of cleanups and fixes are introduced for
SC8180X.
On SC8280XP the additional tsens instances are introduced. Camera
Subsystem and Camera Control Interface (CCI) are added. PMIC die-temp
vadc channels are introduced on the CRD, to allow ADC channels to be
tied to the shared PMIC temp-alarms, to actually report temperature.
On SDM630 USB QMP PHY support is introduced and enabled on the Inforce
IFC6560 board. On the various Sony Xperia XA2 variants WLED is enabled
and configured.
On SM6350 display subsystem interconnects and tsens-based thermal zones
are added. On SM7125 UFS support is added.
On Fairphone FP4, on SM7225, display and GPU are enabled, and firmware
paths are corrected.
SM8150 PCIe controller definitions are corrected.
As with SM8650, the SM8550 the fastrpc compute contexts are marked
dm-coherent, and PCIe controllers are moved to use GIC-ITS. The UFS
controller frequency definition is moved to the generic opp-table.
Touchscreen is enabled on the QRD device.
As usual, a variety of smaller cleanups and corrections to match
DeviceTree bindings and style guidelines are introduced across the
various files.
-----BEGIN PGP SIGNATURE-----
iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmXayZYVHGFuZGVyc3Nv
bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FtLcQAJyCQ/wRZ2BVVr3afFqWaAIQQ4+X
mTywp/1dtWDbLMew2WIcv1KLHVDynsPWYr/AWM3w0kjgbiqr+EzZl18GVAqf53QB
CCkgbLClEKl8NyGQGKWRfp0PF5K/ujv50+6WxwJ+46Sm63odAHe1MZFQQsyuMACn
uP7R9yiKt39ztwXp24KbbS6OKNnxtvqeI2OTYFiQV6kR/AqTONrIedqNhvMfgAw9
jOF5ZkqDTlTqJhcszOkzfBC18bnTLvhKP0TG4YhlUpDwJVIaGVp3vzIzX7PJgVIA
XxbWqc6I91PIPTHCu4gCcklQXLdu3Uc1cBqufiE70+GgDo4+P4nJkSDNeSrOUuQA
NXUULnFyum7U0S3yIQHD2wiUIqRwgwfLJeKe7Z8kya4cCWkcvUBWBw+e8GCADlEI
R22pY4bpJwJYO66TCHT/5A05HjnSh/wY1O56fLepJ5ywGQKX7U71mZsGehSgwp4u
/OuWgRqnMmcyNAZKE/NMFfGUCRLRWwzWTl4VQ1Fiq+JN3jcySFyAm+cW8NXQ3q6y
oDcxx8TyWn+nBS/oErNZ9Q0I7jQun4DzUyYszeBEzffyWPie3KI6KtqlkJGSmK/y
Z1kCOnlJSfDNnRYHR82fNFSuHpIpBYhdSWUduweLwiX36ZfFcZ8QA8eTsDANNgf4
TZflGJSXL8YMBucn
=LM9R
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXhqwQACgkQYKtH/8kJ
Uie8thAAk7/ASn/Q8PcHAEamCk34HFADaVnUpU6OTtQwiBDr3amRx8IfrGqxbW6e
BVZOFnasehDLl68433XrFTQfaRLFxRJEoY5sZ1PFOCZvqoO8IfjawokpjzKzq6PK
0HprU82+CVl9UwYjcAEWD2y/alQ4Q48YUF971q7dzBCTey8gXUZtyW2fk7ZptzR1
utq3rE3zK+WRvijTdHNsjw3qdwoM3K8QrryocKqYqzQM9RKNu2JfJgH1VL+8W70x
eZvASON8wYgByaKke5WrK9k1ZGCj01Qy7bfdv/hzz+DZ+KkvvJce+/gy1zB5klzV
fP6qSP5BP8zTzaQx/pqK3TDb/QMXNndwmWYufAtQ4LE0c5AwDnd9ZJN29yb4ASME
cSUfc0cfrL/JrWlk17FWPo94z9InWBurZg/L8ljS3ms6MWUQcaZjIPrUYz+scAdF
dVlJJrX1eJVNj95q/79DfjNeRgMOzj8E5dm/qGDEM/XxQvCLo3pEWAiauIYRkGFE
NsG1uZsW833gx3M0ZEtGtP9Nl2Mai5gyZjXFa+P5Of9TQ1/FYWghyn7hmfajGqlJ
gQzsBwbJSQv9H40X907NbLE9fULHHfAfTY0SFHaH1U6LmxrGfXpKm44+KKoEABAH
Lkx4k8da0ALK+YsYbXtPkd95zdIUx2567GwJaAZg46QKaBAjk9o=
=+uiX
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm ARM64 DeviceTree updates for v6.9
Four variants of Samsung Galaxy Core Prime and Grand Prime, built on
MSM8916, and the Hardware Development Kit (HDK) for SM8550, are
introduced.
On X Elite audio and compute remoteprocs, IPCC, PCIe, AOSS QMP, SMP2P,
TCSR, USB, display, audio, and soundwire support is introduced, and
enabled across the CRD and QCP devices.
For SM8650 PCIe controllers are moved to GIC-ITS and msi-map-mask is
defined. Missing qlink-logging reserved-memory region is added for the
modem remoteproc. FastRPC compute contexts are marked dma-coherent.
Audio, USB Type-C and PM8010 support is introduced across MTP and QRD
devices.
GPU cooling devices are hooked up across MSM8916, MSM8939, SC8180X,
SDM630, SDM845, SM6115, SM8150, SM8250, SM8350, and SM8550.
UFS PHY clocks are corrected across MSM8996, MSM8998, SC8180X, SC8280XP,
SDM845, SM6115, SM6125, SM8150, SM8250, SM8350, SM8550, and SM8650.
PCI MSI interrupts are wired up across SM8150, SM8250, SM8350, SM8450,
SM8550, SM8650, SC7280, and SC8180X
On IPQ6018 QUP5 I2C, tsens sand thermal zones are defined. The Inline
Crypto Engine (ICE) is enabled for IPQ9574.
On MSM8953 the GPU and its IOMMU is introduced, the reset for the
display subsystem is also wired up.
VLS CLAMP registers are specified for USB3 PHYs on MSM8998, QCM2290, and
SM6115.
USB Type-C port management is enabled on QRB4210 RB2.
On the SA8295P ADP the MAX20411 regulator powering the GPU rails is
introduced and the GPU is enabled. The first PCI instance on SA8540P
Ride is disabled for now, as a fix for the interrupt storm produced here
has not been presented.
On SA8775P the firmware memory map has changed and is updated. Safety
IRQ is added to the Ethernet controller.
On SC7180 UFS support is introduced and the cros-ec-spi is marked as
wakeup source.
For SC7280 capacity and DPC properties are added, cryptobam definition
is improved to work in more firmware environments, more Chrome-specific
properties are moved out from main dtsi, and cros-ec-spi is maked as a
wakeup source. Slimbus definition is added to the platform.
A missing reserved-memory range is added to Fairphone FP5, PMIC GLINK
and Venus are enabled. LEDs are introduced and voltage settings
corrected on the QCM6490 IDP, and RB3gen2 sees the same voltage changes
and GCC protected clocks are introduced to make the board boot properly.
RPMh sleep stats and a variety of cleanups and fixes are introduced for
SC8180X.
On SC8280XP the additional tsens instances are introduced. Camera
Subsystem and Camera Control Interface (CCI) are added. PMIC die-temp
vadc channels are introduced on the CRD, to allow ADC channels to be
tied to the shared PMIC temp-alarms, to actually report temperature.
On SDM630 USB QMP PHY support is introduced and enabled on the Inforce
IFC6560 board. On the various Sony Xperia XA2 variants WLED is enabled
and configured.
On SM6350 display subsystem interconnects and tsens-based thermal zones
are added. On SM7125 UFS support is added.
On Fairphone FP4, on SM7225, display and GPU are enabled, and firmware
paths are corrected.
SM8150 PCIe controller definitions are corrected.
As with SM8650, the SM8550 the fastrpc compute contexts are marked
dm-coherent, and PCIe controllers are moved to use GIC-ITS. The UFS
controller frequency definition is moved to the generic opp-table.
Touchscreen is enabled on the QRD device.
As usual, a variety of smaller cleanups and corrections to match
DeviceTree bindings and style guidelines are introduced across the
various files.
* tag 'qcom-arm64-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (176 commits)
arm64: dts: qcom: sm6115: fix USB PHY configuration
arm64: dts: sm8650: Add msi-map-mask for PCIe nodes
arm64: dts: qcom: replace underscores in node names
dt-bindings: arm: qcom: Add Samsung Galaxy Tab 4 10.1 LTE
arm64: dts: qcom: pm4125: define USB-C related blocks
arm64: dts: qcom: sa8540p-ride: disable pcie2a node
arm64: dts: qcom: sc7280: add slimbus DT node
arm64: dts: qcom: sc7280: Add capacity and DPC properties
arm64: dts: qcom: pmi632: Add PBS client and use in LPG node
arm64: dts: qcom: sm8550: Use GIC-ITS for PCIe0 and PCIe1
arm64: dts: qcom: sm8150: correct PCIe wake-gpios
arm64: dts: qcom: sdm845-db845c: correct PCIe wake-gpios
arm64: dts: qcom: sm7225-fairphone-fp4: Enable display and GPU
arm64: dts: qcom: sm6350: Remove "disabled" state of GMU
arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add fuel gauge
arm64: dts: qcom: sm6350: Add interconnect for MDSS
arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add initial device trees
arm64: dts: qcom: sm8550: Switch UFS from opp-table-hz to opp-v2
arm64: dts: qcom: sc8180x: describe all PCI MSI interrupts
arm64: dts: qcom: minor whitespace cleanup
...
Link: https://lore.kernel.org/r/20240225050146.484422-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The PCI node interrupt-map properties have the wrong size as #address-cells
in the interrupt parent are not accounted for.
The dtc interrupt_map check catches this, but the warning is off because
its dependency, interrupt_provider, is off by default.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240213-arm-dt-cleanups-v1-5-f2dee1292525@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add clock-frequency to MDIO node to set the MDC rate to 6.25Mhz instead
of using the default value of 390KHz from MDIO default divider.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240131022731.2118-1-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
On several QUSB2 Targets, the hs_phy_irq mentioned is actually
qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
to qusb2_phy for such targets.
In actuality, the hs_phy_irq is also present in these targets, but
kept in for debug purposes in hw test environments. This is not
triggered by default and its functionality is mutually exclusive
to that of qusb2_phy interrupt.
Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
Add missing ss_phy_irq on some targets which allows for remote
wakeup to work on a Super Speed link.
Also modify order of interrupts in accordance to bindings update.
Since driver looks up for interrupts by name and not by index, it
is safe to modify order of these interrupts in the DT.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add dedicated compatible for the SDHCI MMC controller, because usage of
generic qcom,sdhci-msm-v4 compatible alone is deprecated.
Cc: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231211085830.25380-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct
node name for the controller instances.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20231206135540.17068-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add node to support the QUP4 SPI controller inside of IPQ8074.
Some devices use this bus to communicate to a Bluetooth controller.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20231123121324.1046164-1-robimarko@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Pass QMP PCI PHY PIPE clocks to the GCC controller so it does not have to
find them by matching globaly by name.
If not passed directly, driver maintains backwards compatibility by then
falling back to global lookup.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231013164025.3541606-2-robimarko@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
While the kernel is booting up, APSS clock / CPU clock will be running
at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
APSS PLL will be configured to the rate based on the opp table and the
source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
consume the GPLL0, with this inclusion, CPU Freq correctly reports that
CPU is running at 800MHz rather than 24MHz.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-8-c8ceb1a37680@quicinc.com
[bjorn: Updated commit message, as requested by Kathiravan]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
SMEM uses lock index 3 of the TCSR Mutex hwlock for allocations
in SMEM region shared by the Host and FW.
Fix the SMEM hwlock index to 3 for IPQ8074.
Cc: stable@vger.kernel.org
Fixes: 42124b947e ("arm64: dts: qcom: ipq8074: add SMEM support")
Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230904172516.479866-4-quic_viswanat@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for each
SoC vendor, following the same scheme that is used on arm64, mips and
riscv. This has been discussed for many years, but so far we never did
this as there was a plan to move the files out of the kernel entirely,
which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along
with their device drivers.
* The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the time.
* Amlogic C3 is a Cortex-A35 based smart IP camera chip
* Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
* Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
* Qualcomm SDX75 is the latest generation modem chip that is used
as a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
* Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the Xuantie
C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those included
there are 39 new board files, but only five more 32-bit this time, probably
a new low:
* Marantec Maveo board based on dhcor imx6ull module
* Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
* Epson Moverio BT-200 AR glasses based on TI OMAP4
* PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
* ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than
we had in the recent releases:
* Three boards based on NXP i.MX8: Emtop SoM & Baseboard,
NXP i.MX8MM EVKB board and i.MX8MP based Gateworks Venice
gw7905-2x device.
* NVIDIA IGX Orin and Jetson Orin Nano boards, both based on
tegra234
* Qualcomm gains support for 6 reference boards on various members
of their IPQ networking SoC series, as well as the Sony Xperia M4
Aqua phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board
on top of the various reference platforms for their new chips.
* Rockchips support for several newer boards: Indiedroid Nova (rk3588),
Edgeble Neural Compute Module 6B (rk3588), FriendlyARM NanoPi R2C
Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn Fastrhino R66S/R68S
(rk3568)
* TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex Verdin
family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
* continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
* support for devicetree overlays on at91, bcm283x
* significant additions to existing SoC support on mediatek, qualcomm,
ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST STM32MP1
As usual, a lot more detail is available in the individual merge
commits.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSdmeUACgkQYKtH/8kJ
UieI5A//bxZXA54htEPXN5V1oIgC4JB4UYkf8fAvtyK4tdaImMn4OTwLD8/sw18X
LQHf1VOLGsGJyNCQ+cUoaBnysr2CXqL/9dA/ARTalqnrKMN/OQjt2wg62n1Ss9Pv
XRlxJABGxAokTO/SuPtOIakSkzwDkuAkIFKfmrNQGcT95XkJXJk3FlMRr84310UG
sl6jP2XFSiLSYm958MMNt+DMhxRmKuyT9gos24KGsb83lZSm9DC2hYimkjd1KF5P
CKeShWeoGoJe+YhnJx6dsDSqVgp1DFLZF1G0auSwjs9rCAKnCDMlz+T2bEzviVDh
XONBNmnOGwPRiBI+1WdzX+pZqMMWINmhIObuODV4ANCSlX3KlSaC2rropEimlW9S
CefvYJ+i7v/BQgMLhKlft0RHhsPU7Pfhfq4PWxaIMAOWA6ZaVczMCpgeUupHIwIQ
lWXZZDlqmTL6SCgkOhEtdP2GGec7YSroq7sscinBaQs1f5pfoW83CNn46gZ9Jh8S
RnXp/+vZ7+RFc15Y0VM82F6a7WN/n0BAqKmqwceDrCpf6ILrBc1lA7NhEvd80wbB
IMg8QNqIzZ9aTOoZmB/1wAXaLClKCE3poTF+Wkd5szN7qe+hKAe1M4w5XvNUO/i/
d0/X5KNA2ykuUxRMdd4lG54VsTJdDCVNaNeaEqasv9JCBBfvuwI=
=X/KE
-----END PGP SIGNATURE-----
Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC devicetree updates from Arnd Bergmann:
"The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for
each SoC vendor, following the same scheme that is used on arm64, mips
and riscv. This has been discussed for many years, but so far we never
did this as there was a plan to move the files out of the kernel
entirely, which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along with
their device drivers.
- The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the
time.
- Amlogic C3 is a Cortex-A35 based smart IP camera chip
- Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
- Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
- Qualcomm SDX75 is the latest generation modem chip that is used as
a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
- Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the
Xuantie C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those
included there are 39 new board files, but only five more 32-bit this
time, probably a new low:
- Marantec Maveo board based on dhcor imx6ull module
- Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
- Epson Moverio BT-200 AR glasses based on TI OMAP4
- PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
- ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than we had
in the recent releases:
- Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM
EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device.
- NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234
- Qualcomm gains support for 6 reference boards on various members of
their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua
phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top
of the various reference platforms for their new chips.
- Rockchips support for several newer boards: Indiedroid Nova
(rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM
NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn
Fastrhino R66S/R68S (rk3568)
- TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex
Verdin family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
- continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
- support for devicetree overlays on at91, bcm283x
- significant additions to existing SoC support on mediatek,
qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST
STM32MP1
As usual, a lot more detail is available in the individual merge
commits"
* tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits)
ARM: mvebu: fix unit address on armada-390-db flash
ARM: dts: Move .dts files to vendor sub-directories
kbuild: Support flat DTBs install
ARM: dts: Add .dts files missing from the build
ARM: dts: allwinner: Use quoted #include
ARM: dts: lan966x: kontron-d10: add PHY interrupts
ARM: dts: lan966x: kontron-d10: fix SPI CS
ARM: dts: lan966x: kontron-d10: fix board reset
ARM: dts: at91: Enable device-tree overlay support for AT91 boards
arm: dts: Enable device-tree overlay support for AT91 boards
arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller
ARM: dts: at91: use generic name for shutdown controller
ARM: dts: BCM5301X: Add cells sizes to PCIe nodes
dt-bindings: firmware: brcm,kona-smc: convert to YAML
riscv: dts: sort makefile entries by directory
riscv: defconfig: enable T-HEAD SoC
MAINTAINERS: add entry for T-HEAD RISC-V SoC
riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
riscv: dts: add initial T-HEAD TH1520 SoC device tree
riscv: Add the T-HEAD SoC family Kconfig option
...
According to bindings, thermal zones must have associated trips as well.
Since we currently dont have CPUFreq support and thus no passive cooling
lets start by defining critical trips to protect the devices against
severe overheating.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
The spi-max-frequency property belongs to SPI devices, not SPI
controller:
ipq8074-hk01.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416123730.300863-2-krzysztof.kozlowski@linaro.org
In IPQ SoCs, bootloader will collect the system RAM contents upon crash
for the post morterm analysis. If we don't reserve the memory region used
by bootloader, obviously linux will consume it and upon next boot on
crash, bootloader will be loaded in the same region, which will lead to
loose some of the data, sometimes we may miss out critical information.
So lets reserve the region used by the bootloader.
Similarly SBL copies some data into the reserved region and it will be
used in the crash scenario. So reserve 1MB for SBL as well.
While at it, drop the size padding in the reserved memory region,
wherever applicable.
Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526110653.27777-4-quic_viswanat@quicinc.com
Like any other Qualcomm SoCs, IPQ8074 and IPQ6018 also supports the
download mode to collect the RAM dumps if system crashes, to perform
the post mortem analysis. Add support for the same.
Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526110653.27777-3-quic_viswanat@quicinc.com
"soc" node is supposed to have unit address:
Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230420063610.11068-2-krzysztof.kozlowski@linaro.org
Add node to support the QUP5 SPI controller inside of IPQ8074.
Some devices use this bus in order to manage external switches.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230426185647.180166-1-robimarko@gmail.com
The property logically makes sense in decimal, and is the standard used
elsewhere.
Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230501212446.2570364-3-ahalaney@redhat.com
Add required cache-level and cache-unified properties to fix warnings
like:
qdu1000-idp.dtb: l3-cache: 'cache-unified' is a required property
qdu1000-idp.dtb: l2-cache: 'cache-level' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416101134.95686-3-krzysztof.kozlowski@linaro.org
Cache level is by convention a decimal number, not hex.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416101134.95686-2-krzysztof.kozlowski@linaro.org
For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI addresses
(0x10200000, 0x20200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses and align
them in a single line.
Fixes: 33057e1672 ("ARM: dts: ipq8074: Add pcie nodes")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-6-manivannan.sadhasivam@linaro.org
The SPMI controller (PMIC Arbiter)) does not use nor allow 'cell-index'
property:
sm8150-microsoft-surface-duo.dtb: spmi@c440000: Unevaluated properties are not allowed ('cell-index' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-1-krzysztof.kozlowski@linaro.org
IPQ8074 has efuses like other Qualcomm SoC-s that are required for
determining various HW quirks which will be required later for CPR etc,
so lets add the QFPROM node for start.
Individidual fuses will be added as they are required.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230123101631.475712-2-robimarko@gmail.com
Current PCIe QMP PHY output name were changed in ("arm64: dts: qcom: Fix
IPQ8074 PCIe PHY nodes") however it did not account for the fact that GCC
driver is relying on the old names to match them as they are being used as
the parent for the gcc_pcie0_pipe_clk and gcc_pcie1_pipe_clk.
This broke parenting as GCC could not find the parent clock, so fix it by
changing to the names that driver is expecting.
Fixes: 942bcd33ed ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113164449.906002-9-robimarko@gmail.com
IPQ8074 comes in 2 silicon versions:
* v1 with 2x Gen2 PCIe ports and QMP PHY-s
* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
v2 is the final and production version that is actually supported by the
kernel, however it looks like PCIe related nodes were added for the v1 SoC.
Finish the PCIe fixup by using the correct compatible, adding missing ATU
register space, declaring max-link-speed, use correct ranges, add missing
clocks and resets.
Fixes: 33057e1672 ("ARM: dts: ipq8074: Add pcie nodes")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113164449.906002-8-robimarko@gmail.com
Add the generic 'max-link-speed' property to describe the Gen2 PCIe link
generation limit.
This allows the generic DWC code to configure the link speed correctly.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113164449.906002-4-robimarko@gmail.com
Current ranges property set in Gen2 PCIe node is incorrect, replace it
with the downstream 5.4 QCA kernel value.
Fixes: 33057e1672 ("ARM: dts: ipq8074: Add pcie nodes")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113164449.906002-3-robimarko@gmail.com
IPQ8074 comes in 2 silicon versions:
* v1 with 2x Gen2 PCIe ports and QMP PHY-s
* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
v2 is the final and production version that is actually supported by the
kernel, however it looks like PCIe related nodes were added for the v1 SoC.
Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
by fixing the Gen3 QMP PHY node first.
Change the compatible to the Gen3 QMP PHY, correct the register space start
and size, add the missing misc PCS register space.
Fixes: 33057e1672 ("ARM: dts: ipq8074: Add pcie nodes")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113164449.906002-2-robimarko@gmail.com
Serdes register space sizes are incorrect, update them to match the
actual sizes from downstream QCA 5.4 kernel.
Fixes: 942bcd33ed ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113164449.906002-1-robimarko@gmail.com
It seems that clock-output-names for the USB3 QMP PHY-s where set without
actually checking what is the GCC clock driver expecting, so clock core
could never actually find the parents for usb0_pipe_clk_src and
usb1_pipe_clk_src clocks in the GCC driver.
So, correct the names to be what the driver expects so that parenting
works.
Before:
gcc_usb0_pipe_clk_src 0 0 0 125000000 0 0 50000 Y
gcc_usb1_pipe_clk_src 0 0 0 125000000 0 0 50000 Y
After:
usb3phy_0_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y
usb0_pipe_clk_src 1 1 0 125000000 0 0 50000 Y
gcc_usb0_pipe_clk 1 1 0 125000000 0 0 50000 Y
usb3phy_1_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y
usb1_pipe_clk_src 1 1 0 125000000 0 0 50000 Y
gcc_usb1_pipe_clk 1 1 0 125000000 0 0 50000 Y
Fixes: 5e09bc51d0 ("arm64: dts: ipq8074: enable USB support")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230108130440.670181-2-robimarko@gmail.com
Add the newly documented SoC compatible to MDIO in order to be able to
validate clocks for it.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114194734.3287854-5-robimarko@gmail.com
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
Make sure all multiline C-style commends begin with just '/*' with
the comment text starting on a new line.
Also, fix up some whitespace within comments.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107145522.6706-8-konrad.dybcio@linaro.org
Pass XO and sleep clocks to the GCC controller so it does not have to
find them by matching globaly by name.
If not passed directly, driver maintains backwards compatibility by then
falling back to global lookup.
Since we are here, set cell numbers in decimal instead of hex.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221030175703.1103224-3-robimarko@gmail.com
APCS now has support for providing the APSS clocks as the child device
for IPQ8074.
So, add the A53 PLL and XO clocks in order to use APCS as the CPU
clocksource for APSS scaling.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220849.339732-4-robimarko@gmail.com
IPQ8074 has a tsens v2.3.0 peripheral which monitors
temperatures around the various subsystems on the
die.
So lets add the tsens and thermal zone nodes, passive
CPU cooling will come in later patches after CPU frequency
scaling is supported.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com
