Commit Graph

8 Commits

Author SHA1 Message Date
Kryštof Černý
aee2eca83f arm64: dts: allwinner: Add disable-wp for boards with micro SD card
Adding disable-wp property for micro SD nodes of Allwinner arm64 devices.
Boards were verified from online pictures/tables
that they have micro SD slots.

Signed-off-by: Kryštof Černý <cleverline1mc@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20240919-b4-nanopineoplus2-fix-mmc0-wp-v2-1-c708a9abc9eb@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-10-26 00:12:35 +08:00
Krzysztof Kozlowski
5dfdedf0de arm64: dts: allwinner: drop underscore in node names
Underscores should not be used in node names (dtc with W=2 warns about
them), so replace them with hyphens.  Use also generic name for pwrseq
node, because generic naming is favored by Devicetree spec.  All the
clocks affected by this change use clock-output-names, so resulting
clock name should not change.  Functional impact checked with comparing
before/after DTBs with dtx_diff and fdtdump.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240317184130.157695-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2024-04-15 23:09:55 +02:00
Robert Marko
08d2061ff9
arm64: dts: allwinner: orangepi-zero-plus: fix PHY mode
Orange Pi Zero Plus uses a Realtek RTL8211E RGMII Gigabit PHY, but its
currently set to plain RGMII mode meaning that it doesn't introduce
delays.

With this setup, TX packets are completely lost and changing the mode to
RGMII-ID so the PHY will add delays internally fixes the issue.

Fixes: a7affb13b2 ("arm64: allwinner: H5: Add Xunlong Orange Pi Zero Plus")
Acked-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Ron Goossens <rgoossens@gmail.com>
Tested-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211117140222.43692-1-robert.marko@sartura.hr
2021-11-17 16:40:50 +01:00
Maxime Ripard
e299e6dd35
ARM: dts: sunxi: Fix the LED node names
According to the LED bindings, the LED node names are supposed to be led
plus an optional suffix. Let's fix our users to use that new scheme.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20210114113538.1233933-6-maxime@cerno.tech
2021-01-18 10:13:16 +01:00
Clément Péron
cabbaed719
arm64: dts: allwinner: unify header comment style
Allwinner device tree files used different comment style for
copyright notice.

Update this to keep a coherency.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-16 11:16:14 +01:00
Clément Péron
b4b8f2c961
arm64: dts: allwinner: Convert license to SPDX identifier
Use a shorter SPDX identifier instead of pasting the
whole license.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-16 11:16:04 +01:00
Maxime Ripard
a4dc791974
ARM: dts: sun8i: h3: Refactor the pinctrl node names
The H3 and H5 have never been converted to the new convention we want to
have for the pinctrl nodes.

Convert them.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25 21:05:42 +01:00
Hauke Mehrtens
a7affb13b2
arm64: allwinner: H5: Add Xunlong Orange Pi Zero Plus
The Xunlong Orange Pi Zero Plus is single board computer.
- H5 Quad-core 64-bit Cortex-A53
- 512MB DDR3
- microSD slot
- Debug TTL UART
- 1000M/100M/10M Ethernet RJ45
- Realtek RTL8189FTV
- Spi flash (2MB)
- One USB 2.0 HOST, One USB 2.0 OTG

This is based on a patch from armbian:
https://github.com/armbian/build/blob/master/patch/kernel/sunxi-next/sunxi-add-orangepi-zero-plus.patch

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-20 11:43:41 +01:00