Core changes:
- Open code PINCTRL_FUNCTION_DESC() instead of defining
a complex macro only used in one place.
- Add pinmux_generic_add_pinfunction() helper and
use this in a few drivers.
New drivers:
- Amlogic S7, S7D and S6 pin control support.
- Eswin EIC7700 pin control support.
- Qualcomm PMIV0104, PM7550 and Milos pin control
support.
Because of unhelpful numbering schemes, the Qualcomm
driver now needs to start to rely on SoC codenames.
- STM32 HDP pin control support.
- Mediatek MT8189 pin control support.
Improvements:
- Switch remaining pin control drivers over to the
new GPIO set callback that provides a return value.
- Support RSVD (reserved) pins in the STM32 driver.
- Move many fixed assignments over to pinctrl_desc
definitions.
- Handle multiple TLMM regions in the Qualcomm driver.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmiN/SkACgkQQRCzN7AZ
XXPeGw/7BMBf6Uuhs39qHjnLUUgp/H2yzRV7JB3Q99AZh++7mK0z4MchsZfjvXmv
Ql2ADPHzmP9AJwSor/Ssvn4SrPwvC62IFBznB4eqPIL4UgWuIEYSJQNFMbZniFex
kd8+7GAK7K5R5ReIWfUCs3xusO4+MShXZNKkWVaQZT+603kVznADGANBbEkOnXxY
06JKEo++QuChvLMckGOzyW8zAOV68YM2VYaZkuxxCIaIwKoNzGPKDt8NpPvaIijE
S6EhrhRiM595Jt+qAC6lWtwGnFL5DI69Au2IDzaOSyamNLBoA/bmUu9UWB6/HxW2
yOhDW3DbXOB2xhUORlwCBtGsDyxLB9cIyBMjr6JantwPHdz8dzetxaTrwpuNdBQ+
+BgTodEuZf+TXroUQZ5sPRycEKZm1rtO7ctiZ5bG+CtP8qXcc+enMmC8BSCNCWzl
bMOLsvP4ZMOuVU2ryOvhqKnbWxLS2RV5nHChtTF2JoE4ZX0dN/dhvGOe/A4dINhG
3Nb+ETmyEnid9PIPARYNy/7BkT92eEUQJlbI9qeU1AojGmRRQLS3+mJD9VcFSe1F
/sjp5OYL2M/7SUpqBtlapLXN014gSAVV7zzQThndOYf8RJgohQkOWZsZUx7jyieA
4VYQzLWKAfP/IdOnKzM/8mAHw6VT9gJiWtNsc8ZdeYMwhYGSbbM=
=hEj7
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Nothing stands out, apart from maybe the interesting Eswin EIC7700, a
RISC-V SoC I've never seen before.
Core changes:
- Open code PINCTRL_FUNCTION_DESC() instead of defining a complex
macro only used in one place
- Add pinmux_generic_add_pinfunction() helper and use this in a few
drivers
New drivers:
- Amlogic S7, S7D and S6 pin control support
- Eswin EIC7700 pin control support
- Qualcomm PMIV0104, PM7550 and Milos pin control support
Because of unhelpful numbering schemes, the Qualcomm driver now
needs to start to rely on SoC codenames
- STM32 HDP pin control support
- Mediatek MT8189 pin control support
Improvements:
- Switch remaining pin control drivers over to the new GPIO set
callback that provides a return value
- Support RSVD (reserved) pins in the STM32 driver
- Move many fixed assignments over to pinctrl_desc definitions
- Handle multiple TLMM regions in the Qualcomm driver"
* tag 'pinctrl-v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (105 commits)
pinctrl: mediatek: Add pinctrl driver for mt8189
dt-bindings: pinctrl: mediatek: Add support for mt8189
pinctrl: aspeed-g6: Add PCIe RC PERST pin group
pinctrl: ingenic: use pinmux_generic_add_pinfunction()
pinctrl: keembay: use pinmux_generic_add_pinfunction()
pinctrl: mediatek: moore: use pinmux_generic_add_pinfunction()
pinctrl: airoha: use pinmux_generic_add_pinfunction()
pinctrl: equilibrium: use pinmux_generic_add_pinfunction()
pinctrl: provide pinmux_generic_add_pinfunction()
pinctrl: pinmux: open-code PINCTRL_FUNCTION_DESC()
pinctrl: ma35: use new GPIO line value setter callbacks
MAINTAINERS: add Clément Le Goffic as STM32 HDP maintainer
pinctrl: stm32: Introduce HDP driver
dt-bindings: pinctrl: stm32: Introduce HDP
pinctrl: qcom: Add Milos pinctrl driver
dt-bindings: pinctrl: document the Milos Top Level Mode Multiplexer
pinctrl: qcom: spmi: Add PM7550
dt-bindings: pinctrl: qcom,pmic-gpio: Add PM7550 support
pinctrl: qcom: spmi: Add PMIV0104
dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIV0104 support
...
Another small set of code changes for the 32-bit Arm platforms, and a
trivial update to the Kconfig entry for the arm64 TI K3 chip.
Andrew Davis cleans up the system reset handling, which touches a couple
of platforms.
The mediatek platform needs some code changes to support multiprocessing
in the newly added support for the old mt6572 chip.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmiD8/EACgkQmmx57+YA
GNmGsBAApv+7kWvy94wulfAptZTfXTcGBB174IVdAG9XX93eWVcPNzlbTv34BYa9
aMHuRrrO4ttRaHgdtNqT/gZgrojqmhK/GMSV6Sun770tDLMNrVUtcLs7iNmU6VvD
Va873hdI2nXvxZCVrDfkS7fQWjqx4L3L2wW9AuX7rs3xEUALuIhYoYoCqF+NzRTL
V6rtPUZAoQ/6b4nRopCH3aTaxJOy20mYjEFI9O6WQjAYmd1V+jATJ4vNxIBJp8W+
fVOfgVVqULEaapaGL96x8UQegRBnSabbKTYgEcmFDqQKaslxmuS+sD5d6N+vhWFX
3BQyOjjDgXu5AlL6fIJV0t3JvZ8ud4rNnyp62m6vzppYcBRnzNmdp5WDgKEtyd1G
FbBF0cQx4KqfswtmcycHJj3fmYccsqD2jvc35+8tFP5vjrzOV2THWLAA+6maFUTe
BI8+y2/EIHFZ1rwDoMK/zuiesMm7G64Tf4UkH14wV0RohqNrU1ZapTX3WbERmV7T
miRxvrK4Vh4B31I11PAHYBSw7KRPIf94MzUy1mPvQ7EjvYDdW1s2Ufygm3+33j3R
aXYhcUjNkenSH0GyYTyycLFxTklAERLroRxz8h6j+PHIpbxulX+wG/xwd1v2JTsE
TKGV6jBecaE1A5OJWxVEl6P9MOizIe1BDTaLxL08Nf6bp+OlLUs=
=SZ0j
-----END PGP SIGNATURE-----
Merge tag 'soc-arm-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC code updates from Arnd Bergmann:
"Another small set of code changes for the 32-bit Arm platforms, and a
trivial update to the Kconfig entry for the arm64 TI K3 chip.
Andrew Davis cleans up the system reset handling, which touches a
couple of platforms.
The mediatek platform needs some code changes to support
multiprocessing in the newly added support for the old mt6572 chip"
* tag 'soc-arm-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: sa110/gpio: convert set_multiple() to returning an integer
ARM: rockchip: fix kernel hang during smp initialization
ARM: mediatek: add MT6572 smp bring up code
ARM: mediatek: add board_dt_compat entry for the MT6572 SoC
ARM: tegra: Use I/O memcpy to write to IRAM
arm: orion: use string choices helper
ARM: Switch to new sys-off handler API
arm64: Kconfig.platforms: remove useless select for ARCH_K3
Sophgo:
Add support for Duo Module 01 Evaluation Board.
This board uses SG2000(old codename CV181xH),
which is dual-arch, RISC-V and ARM64. This
patch add the support for ARM64.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
-----BEGIN PGP SIGNATURE-----
iQGzBAABCgAdFiEEdoBX2jyDC9ZCTwZjDCzASqG0i0IFAmiAiNIACgkQDCzASqG0
i0KaPgv/Zbe5hJ869PocVXmt1+lHnMMh6bTANXlZO4G3NcjBOvCWF9rZaqY7Tb0w
ekLbSTnhBqcwix62FxDuOubsgAGrj/r5ejnPkLI/Ksst+81DDcgtxmU4YHjV/M92
win6fsrS5LppqS7+6lGAhN0Uz48K07j9URW2JtollpH0GyrzNo1r4YwfkUA38X+b
e+Eia0bvz8KU1aKPLgmx+dk/qjhDvvlWjNrroVyJAkUYM5AofSSzneo2hgM6FA0k
1LYZRwLDpbaJjMnBvAFT2Dqg3Mr+84PyHb7d+58lV4BYOzkA/wM6DGuDqD61dt4K
+pxflhrZsXp+a9SjnY6oecGy1srKDPhX8l6mRdwt3ISAFJ/6nKTEXk36sO1T9atq
mfpwDwDklhVwpvmk9JAWeTCX/XMBgivVDdUE9sRTzBqPIlBtSVHjS8W7e5nExbv8
yovIIKE4OLKn40ubcYM8Km0L3XF6VpoNFlPkxwrXDyf7FVzdHTphz0aW8CXIO0dP
4W1vqUcP
=v6O6
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmiBQ8MACgkQmmx57+YA
GNmgUQ/+JJHLhDUdfI6abJSs42ZS7yue8DRbSYi/h3RDkj7LutwbrTrOZ7Dg0uom
txv2dUPtmW2DIvJkRrBfNeF9bMt9oh0/0cLuf9QL8mLWHaSg9aAwmBDbw8EaKCy1
iwxwAhRxDg1bF6eB0QDE0f2+wuBBiR2ymWcpLgHw3pZw1Ao7R8nvV0UvrxUKJaMa
8GpenYRnVrxHtwtSLS+eFQUvxFGb8SYdHxhZYL3U34XduugK3xNv2+KoFdQvro6R
vEMnpR6USo2mV4RW7GTwJkPmQ/w0fMZF806bPNu7KhrC3DLmVnU6YuBDopJYrPvU
babwfughoSn7cz733gDSPuzkoNkjXiCZLQW9wSv+gGgYHK6NpjtHfZGkEfcRpXT1
G9Yb/H948BtLM4FxenFh+5VEvp63giN3hTIw/0JauFWEu4rTmN6sMLT1ibLDeUZV
zIfItosgFF+EjuGqgruR8dJ9wKowIR9DY8MxhWQ5Wu1WNl+KKMtln/bFIu9hgvRi
0WqgqPr6Vq5buHKaqHAz0tj8dR7yxBZvDijQfzzb0xrLgBXx35c7aX1aKWdxWbYZ
Y29KQLxsvr0AWs0tafmQ42M0l03QAB1voACn25rIQaU4b4Tub9W18GkA0V6Mmjno
diqH51MQy1haCJRZUMEyAUnmtOXlRw685Jzy1z5BekUJIhTGQfg=
=SQbL
-----END PGP SIGNATURE-----
Merge tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/newsoc
ARM Devicetrees for v6.17
Sophgo:
Add support for Duo Module 01 Evaluation Board.
This board uses SG2000(old codename CV181xH),
which is dual-arch, RISC-V and ARM64. This
patch add the support for ARM64.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux:
arm64: defconfig: Enable rudimentary Sophgo SG2000 support
arm64: Add SOPHGO SOC family Kconfig support
arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
arm64: dts: sophgo: Add Duo Module 01
arm64: dts: sophgo: Add initial SG2000 SoC device tree
Link: https://lore.kernel.org/r/MAUPR01MB11072C4B088AAC02268044E95FE5FA@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
First user will be Aarch64 core within SG2000 SoC.
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250612132844.767216-6-alexander.sverdlin@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Support for the AX3000 SoC, from Harshit Shah <hshah@axiado.com>:
The AX3000 is a multi-core system-on-chip featuring four ARM Cortex-A53
cores, secure vault, hardware firewall, and AI acceleration engines. This
initial support enables basic bring-up of the SoC and evaluation platform
with CPU, timer, UART, and I3C functionality.
The series begins by adding the "axiado" vendor prefix and compatible
strings for the SoC and board. It then introduces the device tree files
and minimal ARCH_AXIADO platform support in arm64.
* newsoc/axiado:
MAINTAINERS: Add entry for Axiado
arm64: defconfig: enable the Axiado family
arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
arm64: add Axiado SoC family
dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
dt-bindings: serial: cdns: add Axiado AX3000 UART controller
dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
dt-bindings: gpio: cdns: convert to YAML
dt-bindings: arm: axiado: add AX3000 EVK compatible strings
dt-bindings: vendor-prefixes: Add Axiado Corporation
Add ARCH_AXIADO for the support of the Axiado SoC for arm64 architecture.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Patches from Peter Chen <peter.chen@cixtech.com>:
Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC.
Orion O6 is the Arm V9 Motherboard built by Radxa. You could find brief
introduction for SoC and related boards at:
https://radxa.com/products/orion/o6#overview
Currently, to run upstream kernel at Orion O6 board, you need to
use BIOS released by Radxa, and add "clk_ignore_unused=1" at bootargs.
https://docs.radxa.com/en/orion/o6/bios/install-bios
In this series, we add initial SoC and board support for Kernel building.
Since mailbox is used for SCMI clock communication, mailbox driver is added
in this series for the minimum SoC support.
Patch 1-2: add dt-binding doc for CIX and its sky1 SoC
Patch 3: add Arm64 build support
Patch 4-5: add CIX mailbox driver which needs to support SCMI clock protocol.
Patch 6: add Arm64 defconfig support
Patch 7-8: add initial dts support for SoC and Orion O6 board
Patch 9: add MAINTAINERS entry
* newsoc/cix-p1:
MAINTAINERS: Add CIX SoC maintainer entry
arm64: dts: cix: Add sky1 base dts initial support
dt-bindings: clock: cix: Add CIX sky1 scmi clock id
arm64: defconfig: Enable CIX SoC
mailbox: add CIX mailbox driver
dt-bindings: mailbox: add cix,sky1-mbox
arm64: Kconfig: add ARCH_CIX for cix silicons
dt-bindings: arm: add CIX P1 (SKY1) SoC
dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add ability to build pinctrl for stm32mp257 as a kernel module.
Add kernel-doc to the exported symbols.
Signed-off-by: Stephane Danieau <stephane.danieau@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Link: https://lore.kernel.org/20250610143042.295376-5-antonio.borneo@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The HAVE_PWRCTRL symbol has been renamed to reflect the pwrctrl framework
name. Switch to the non-deprecated symbol.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://patch.msgid.link/20250402132634.18065-5-johan+linaro@kernel.org
Highlights:
----------
- MPU:
- STM32MP13:
- Add thermal support.
- Add Priva E-Measuringbox board support based on sTM32MP133C SoC.
It embeds Ethernet RMII with TI phy, SDCard, eMMC and some
sensors.
- Add support for DHCOR SoM and DHSBC rev.200 board:
TPM interrupts and gpio reset + LDO2/LDO5 support.
- STMP32MP15:
- Add new Octavo support: LXA FairyTux 2 based on OSD32MP153C SiP.
It contains eMMC for storage, a gigabit Ethernet, a CAN bus and
a RS485 transceiver.
- Add Plymovent AQM board based on STM32MP151 SoC. It embeds:
ETH RMII, WLAN, BT, Sensors (CO2, PM, pressure), Audio (I2S),
Storage (SDCard, eMMC).
- STM32MP25:
- Add STM32MP257F Discovery board: It embeds a STM32MP257FAL SoC,
with 4GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH,
wifi/BT combo, DSI HDMI, LVDS connector ...
- Introduce STM32MP23 SoC and add STM32MP235F Discovery board:
It embeds a STM32MP235FAK SoC, with 4GB of LPDDR4, 2*USB typeA,
1*USB3 typeC, 1*ETH, wifi/BT combo, DSI HDMI, LVDS connector ...
- Introduce STM32MP21 SoC and STM32MP215F discovery board:
It embeds a STM32MP235FAN SoC, with 2GB of LPDDR4,
1*USB2 peripheral bus powered typeC, 1*ETH, wifi/BT combo,
LCD 18bit connector, CSI camera connector, ...
-----BEGIN PGP SIGNATURE-----
iQJRBAABCgA7FiEEctl9+nxzUSUqdELdf5rJavIecIUFAmfRrqodHGFsZXhhbmRy
ZS50b3JndWVAZm9zcy5zdC5jb20ACgkQf5rJavIecIX6Jw/+M+2cLmsaxiRI8My9
tJMOQqAAURUXxqmHDhD5PSYpMNvkVspJfBKZEWujgkSXHB3MVxwkpat3oirLuS8u
uyqcwE+wybHHRqDjIy1/jSkldET2xwkY9oVRJ3LKPNlvh/eSX+OgAXWFHQ6X2VZ/
SAHjXTmJmCTDzzCPh8R/WSSDThdq1Ce0T83BVkbnhq4S20tcYoyWC1RhYSUvFx/R
rGY9jkXZt//6aaY3Bgifevcf1DAKFguFNL5R16mAg/tJa5CTv4Xyau09fnCZYsUj
4ldNmGn4o8cku7svtSYwPwygadGOoVbUTjGFQo0CQuhbCM1MocYhcCPFEVTNnzDw
UaNZ5i1ipq6h5cTz801QOecJEBQdNcrKrB8FcQQm2spA5E5vKZwCSmR4ajtGAr5E
AhE9BXY8qWDIDPD7Gy5LHGS94juPWGqX3hOYYfBNLVGhEBif39I1Qg8Gbp1H33nX
eQ3cDaj1QtYSKCv3Da/zXJkreEUzsJRFcVBWPGyuw1yjgMFPzOf74qPESc38fjWP
nZfqSJVwb5dVpdUgdnouVaBcutyMSobWFh6tFdyycINs9TOGE4YROyq4+74m03D8
ErUS4cm0bTssXZvA5eDVa8taeKo2U730WNktpRTQNaJ9JQMGDyNmdm/3Tun4C4wU
8+UllZywmTUM/rwfBrN6Fq9FN1M=
=C3kj
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v6.15-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.15, round 1
Highlights:
----------
- MPU:
- STM32MP13:
- Add thermal support.
- Add Priva E-Measuringbox board support based on sTM32MP133C SoC.
It embeds Ethernet RMII with TI phy, SDCard, eMMC and some
sensors.
- Add support for DHCOR SoM and DHSBC rev.200 board:
TPM interrupts and gpio reset + LDO2/LDO5 support.
- STMP32MP15:
- Add new Octavo support: LXA FairyTux 2 based on OSD32MP153C SiP.
It contains eMMC for storage, a gigabit Ethernet, a CAN bus and
a RS485 transceiver.
- Add Plymovent AQM board based on STM32MP151 SoC. It embeds:
ETH RMII, WLAN, BT, Sensors (CO2, PM, pressure), Audio (I2S),
Storage (SDCard, eMMC).
- STM32MP25:
- Add STM32MP257F Discovery board: It embeds a STM32MP257FAL SoC,
with 4GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH,
wifi/BT combo, DSI HDMI, LVDS connector ...
- Introduce STM32MP23 SoC and add STM32MP235F Discovery board:
It embeds a STM32MP235FAK SoC, with 4GB of LPDDR4, 2*USB typeA,
1*USB3 typeC, 1*ETH, wifi/BT combo, DSI HDMI, LVDS connector ...
- Introduce STM32MP21 SoC and STM32MP215F discovery board:
It embeds a STM32MP235FAN SoC, with 2GB of LPDDR4,
1*USB2 peripheral bus powered typeC, 1*ETH, wifi/BT combo,
LCD 18bit connector, CSI camera connector, ...
* tag 'stm32-dt-for-v6.15-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (26 commits)
arm64: dts: st: add stm32mp215f-dk board support
dt-bindings: stm32: document stm32mp215f-dk board
arm64: dts: st: introduce stm32mp21 SoCs family
arm64: dts: st: add stm32mp235f-dk board support
dt-bindings: stm32: document stm32mp235f-dk board
arm64: dts: st: introduce stm32mp23 SoCs family
dt-bindings: stm32: add STM32MP21 and STM32MP23 compatibles for syscon
arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP21/STM32MP23 SoCs family
arm64: dts: st: add stm32mp257f-dk board support
dt-bindings: stm32: document stm32mp257f-dk board
ARM: dts: stm32: Add Plymovent AQM devicetree
ARM: dts: stm32: Add pinmux groups for Plymovent AQM board
dt-bindings: arm: stm32: Add Plymovent AQM board
dt-bindings: sound: convert ICS-43432 binding to YAML
ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC rev.200 board
ARM: dts: stm32: use IRQ_TYPE_EDGE_FALLING on stm32mp157c-dk2
ARM: dts: stm32: add usr3 LED node to stm32f769-disco
ARM: dts: stm32: rename LEDs nodes for stm32f769-disco
ARM: dts: stm32: add push button to stm32f746 Discovery board
ARM: dts: stm32: add led to stm32f746 Discovery board
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Expand config ARCH_STM32 with two new SoCs families:
- STM32MP21 SoCs family, which is composed of STM32MP211, STM32MP213 and
STM32MP215 SoCs;
- STM32MP23 SoCs family, which is composed of STM32MP231, STM32MP233 and
STM32MP235 SoCs.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-3-1a628c1580c7@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Update the description and contextually the help text of
CONFIG_ARCH_VEXPRESS to reflect the inclusion of all ARM Ltd Platforms.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Message-Id: <20250221180349.1413089-2-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Two new SoC families are added here, with devicetree files and
a little bit of infrastructure to allow booting:
- Blaize BLZP1600 is an AI chip using custom GSP (Graph Streaming
Processor) cores for computation, and two small Cortex-A53 cores
that run the operating system.
- SpacemiT K1 is a 64-bit RISC-V chip, using eight custom RVA22
compatible CPU cores with vector support.
Also marketed at AI applications, it has a much slower NPU compared
to BLZP1600, but in turn focuses on the CPU performance
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmeSd7cACgkQYKtH/8kJ
UienxxAAoUMAWex/k5gWfg3DdvDrleXydjYzIm6DBIad1kxHYy/gvEuQAgV9vxqb
tQ763NKRLekmwv+CX+S47PjrMHgqqwtch5If8ixd50gYSZPukJmuCTkthMu1qBb9
/zi0LXg3cViPQBAY0MwCQMzukRHsqmBzaUSle6bM1yDHhHAmcz88Iqs/LttJOnYk
M/+ybxYoUdVmPI+Nt3e8hxlecfU2oM0S1hoStvdsA0fpuLfEBF8WpF7DnkSphT10
JqVysB3FTF0PYXyBodcuh37iCCObAFVAUT/ZvKO3+Qo/rI2IseP8lSeAV84JP/5S
w4MqpGhFecICBEWJ9h0FnbSI2NyON8uz23R+va6YAtTxuPL2Loq4HwvxXh5H5imC
sxZ0SEnkwFQ7DJ10nV00FXlmKZ7+Ax0WLoboNHWYxdAfqhgcZ8q8gi/+WTETTBog
jnTnWjscuEA5QTNfOP0AqUtVbWQOj09wLsiceJc8G5jpbe9WaZJy1yzXaCNu2hZV
2x+2UT31Y6G2Poxee8Ti4u1ljieJh5BmD1Ts81P8EpAC0JsVyJ3HtouYeBHcBPoj
HXmdGDPN8bS0Ugu7iFu3GO+TPcBzUw1ZND8L3QbBesb/oFK0455ARkVXO2nazP4p
4s/iGWbGAKIyKPOdYGaiSXmbXurx99pOVY6G8ccqkNf+17MfTgE=
=clzA
-----END PGP SIGNATURE-----
Merge tag 'soc-new-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new SoC support from Arnd Bergmann:
"Two new SoC families are added here, with devicetree files and a
little bit of infrastructure to allow booting:
- Blaize BLZP1600 is an AI chip using custom GSP (Graph Streaming
Processor) cores for computation, and two small Cortex-A53 cores
that run the operating system.
- SpacemiT K1 is a 64-bit RISC-V chip, using eight custom RVA22
compatible CPU cores with vector support.
Also marketed at AI applications, it has a much slower NPU compared
to BLZP1600, but in turn focuses on the CPU performance"
* tag 'soc-new-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
riscv: dts: spacemit: move aliases to board dts
riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3
riscv: defconfig: enable SpacemiT SoC
riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree
riscv: dts: add initial SpacemiT K1 SoC device tree
riscv: add SpacemiT SoC family Kconfig support
dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible
dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC
dt-bindings: timer: Add SpacemiT K1 CLINT
dt-bindings: riscv: add SpacemiT K1 bindings
dt-bindings: riscv: Add SpacemiT X60 compatibles
MAINTAINERS: setup support for SpacemiT SoC tree
MAINTAINER: Add entry for Blaize SoC
arm64: defconfig: Enable Blaize BLZP1600 platform
arm64: dts: Add initial support for Blaize BLZP1600 CB2
arm64: Add Blaize BLZP1600 SoC family
dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
dt-bindings: Add Blaize vendor prefix
Add module build support in Kconfig for the TI SCI interrupt aggregator
driver. The driver's default build is built-in and it also depends on
ARCH_K3 as the driver uses some 64 bit ops and should only be built for
64-bit platforms.
Signed-off-by: Nicolas Frayer <nfrayer@baylibre.com>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/all/20241224-timodules-v4-2-c5e010f58e2c@baylibre.com
Add module build support in Kconfig for the TI SCI interrupt router
driver. This driver depends on the TI sci firmware driver which aready
supports module build.
Signed-off-by: Nicolas Frayer <nfrayer@baylibre.com>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/all/20241224-timodules-v4-1-c5e010f58e2c@baylibre.com
Add ARCH_BLAIZE SoC family to the arm64 architecture to
support the BLZP1600 System-On-Module and the Carrier-Board-2
development board.
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
Reviewed-by: Matt Redfearn <matt.redfearn@blaize.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Apple's A7-A11 SoC is now supported, so the original help text is no longer
accurate.
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
- Core:
- Provide a new mechanism to create interrupt domains. The existing
interfaces have already too many parameters and it's a pain to expand
any of this for new required functionality.
The new function takes a pointer to a data structure as argument. The
data structure combines all existing parameters and allows for easy
extension.
The first extension for this is to handle the instantiation of
generic interrupt chips at the core level and to allow drivers to
provide extra init/exit callbacks.
This is necessary to do the full interrupt chip initialization before
the new domain is published, so that concurrent usage sites won't see
a half initialized interrupt domain. Similar problems exist on
teardown.
This has turned out to be a real problem due to the deferred and
parallel probing which was added in recent years.
Handling this at the core level allows to remove quite some accrued
boilerplate code in existing drivers and avoids horrible workarounds
at the driver level.
- The usual small improvements all over the place
- Drivers
- Add support for LAN966x OIC and RZ/Five SoC
- Split the STM ExtI driver into a microcontroller and a SMP version to
allow building the latter as a module for multi-platform kernels.
- Enable MSI support for Armada 370XP on platforms which do not support
IPIs.
- The usual small fixes and enhancements all over the place.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmaVJbUTHHRnbHhAbGlu
dXRyb25peC5kZQAKCRCmGPVMDXSYoXTuD/9Tc9BhY5CW7HQkdPQu2Db1O+esprkQ
Uo9lMpTTpPiy9btg4LONzLf4mjbufZpyKBxkRWoZFO0Zj5q4UE9NZYh7EcxrF5Tl
CIFJmyteLsYuOyCmPrtSDSovonXjQKYBE3u2LVJNNkwEkhYbYW9sqIKeT8nneLv6
53gd28ESFUEUjHNTblw/eXviweyUKSXc0qyg+3hgZQPMoh9RkdkEPvyaw9Y/s5Ce
FelLLxzMqX86dR2TJMLqiaGiMpUu/kl+Yz2m5c77TwA2D68qjhHywbtKtlH7b3C6
LMHu2dMrrKSJrLL8roVIYJdHAd1TKWVdnYhqv9WBHFTu1sDuztpR44mewbo8exUU
L2RgVSGYNmeFC3p4wztWYSQfIVa9uOg7+TnJJdh7G0jLIeKM/TbufWqDAJAuoVPL
QhGbZ5xNbZJZ8bvhhItjxpRN/kPs44p3mUGyRJBQzm+mDN118bqfmQzhLcwRbfE2
smp73SQzg9alG2rGdNVEqkKmp8zhg2Crx2VCeVdgbeOxWQRet9zLWcp4FfCEUE9e
eK3iEi8z+rmwafaf3rsxYdrdIRLaUmcni0v7R/16cJH/Cs7bU3Re8XyGhevo3lsO
pJiP5wZDxbckwXNpLm3S/qPDW7vSCnuFPF7QmOvC3a70PsD+E4NKUgiwJuHtn/ZV
pFBKzbQgCsowQA==
=QCRH
-----END PGP SIGNATURE-----
Merge tag 'irq-core-2024-07-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull interrupt subsystem updates from Thomas Gleixner:
"Core:
- Provide a new mechanism to create interrupt domains. The existing
interfaces have already too many parameters and it's a pain to
expand any of this for new required functionality.
The new function takes a pointer to a data structure as argument.
The data structure combines all existing parameters and allows for
easy extension.
The first extension for this is to handle the instantiation of
generic interrupt chips at the core level and to allow drivers to
provide extra init/exit callbacks.
This is necessary to do the full interrupt chip initialization
before the new domain is published, so that concurrent usage sites
won't see a half initialized interrupt domain. Similar problems
exist on teardown.
This has turned out to be a real problem due to the deferred and
parallel probing which was added in recent years.
Handling this at the core level allows to remove quite some accrued
boilerplate code in existing drivers and avoids horrible
workarounds at the driver level.
- The usual small improvements all over the place
Drivers:
- Add support for LAN966x OIC and RZ/Five SoC
- Split the STM ExtI driver into a microcontroller and a SMP version
to allow building the latter as a module for multi-platform
kernels
- Enable MSI support for Armada 370XP on platforms which do not
support IPIs
- The usual small fixes and enhancements all over the place"
* tag 'irq-core-2024-07-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (59 commits)
irqdomain: Fix the kernel-doc and plug it into Documentation
genirq: Set IRQF_COND_ONESHOT in request_irq()
irqchip/imx-irqsteer: Handle runtime power management correctly
irqchip/gic-v3: Pass #redistributor-regions to gic_of_setup_kvm_info()
irqchip/bcm2835: Enable SKIP_SET_WAKE and MASK_ON_SUSPEND
irqchip/gic-v4: Make sure a VPE is locked when VMAPP is issued
irqchip/gic-v4: Substitute vmovp_lock for a per-VM lock
irqchip/gic-v4: Always configure affinity on VPE activation
Revert "irqchip/dw-apb-ictl: Support building as module"
Revert "Loongarch: Support loongarch avec"
arm64: Kconfig: Allow build irq-stm32mp-exti driver as module
ARM: stm32: Allow build irq-stm32mp-exti driver as module
irqchip/stm32mp-exti: Allow building as module
irqchip/stm32mp-exti: Rename internal symbols
irqchip/stm32-exti: Split MCU and MPU code
arm64: Kconfig: Select STM32MP_EXTI on STM32 platforms
ARM: stm32: Use different EXTI driver on ARMv7m and ARMv7a
irqchip/stm32-exti: Add CONFIG_STM32MP_EXTI
irqchip/dw-apb-ictl: Support building as module
irqchip/riscv-aplic: Simplify the initialization code
...
- fix an invalid pointer dereference in error path in pwrseq core
- reduce the Kconfig noise from PCI pwrctl choices
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEFp3rbAvDxGAT0sefEacuoBRx13IFAmaaMYkACgkQEacuoBRx
13L0Uw/+JdFxMWwQYKwWs84rKaALFtH4+vKzdZlyonGtTCl8X4wr5JX/jqfjBPof
kO8FIKTIofWiiYkL3A5hvZbfuG9aINzOwle5nYhlSyeR5JN/ZJwVOKzfkFF1vcgK
XJdxBZjD8wIB/foouleLH1+DhQu5d9BuB+NsANCcVo4IqAupK618NEVwTqRmQEPf
M4JdmzVTRSVVnKS9RQ8MbXotfUSAI7GuvSCd+xs5SdTlBcgNNTLx4PUWhcLsSY5t
oJ1TCx4a7MrDaFxjt8IvtsfGl0F5+0GNljxvcgSC/bckTzP6WAJJnCf8EIPpq95z
HPx+7fvyKoScZbup+s2HEbRsqLUDQYFyZ8BjbkLBVn0NZSeJngFyEb2+A4JM/zK2
T2gGQk1Xe9HRwsWwi6Gd5wsL6kcknWdedh1B5m5zss2nIGXxO6Vw0Gz7U1dluS/P
x/Olg2Le4oOahyFnsY4byG9hpO2898m/QHs7NMeCDZA3BEdXP2/+eVlASL6JZ2hl
vRU8s6eheCBaI2iAUPF9Lc9+qtY4ry7b3DqCHDj11xxq+i4IwYErxs6ClsgpPBWZ
l/VEPOFJYzFi1Y448uzn5vNPjPE7AsKn2Fl5ZERl7wTi4x8ZlJpVKiA3Cj3OPW1A
hsuEOMJIVyZFEimexoIWK9sky9tY3mHsdhiE/AsF43Bj3aICTQE=
=I1ot
-----END PGP SIGNATURE-----
Merge tag 'pwrseq-fixes-for-v6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
Pull power sequencing fixes from Bartosz Golaszewski:
"There's one fix for an invalid pointer dereference in error path
reported by smatch and two patches that address the noisy config
choices you reported earlier this week.
Summary:
- fix an invalid pointer dereference in error path in pwrseq core
- reduce the Kconfig noise from PCI pwrctl choices"
* tag 'pwrseq-fixes-for-v6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux:
arm64: qcom: don't select HAVE_PWRCTL when PCI=n
Kconfig: reduce the amount of power sequencing noise
power: sequencing: fix an invalid pointer dereference in error path
The new HAVE_PWRCTL option is defined in the PCI subsystem, so
selecting it unconditionally when PCI is disabled causes a harmless
warning:
WARNING: unmet direct dependencies detected for HAVE_PWRCTL
Depends on [n]: PCI [=n]
Selected by [y]:
- ARCH_QCOM [=y]
Add 'if PCI' in the qualcomm platform to hide the warning.
Fixes: ed70aaac7c ("Kconfig: reduce the amount of power sequencing noise")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Kconfig will ask the user twice about power sequencing: once for the QCom
WCN power sequencing driver and then again for the PCI power control
driver using it.
Let's automate the selection of PCI_PWRCTL by introducing a new hidden
symbol: HAVE_PWRCTL which should be selected by all platforms that have
the need to include PCI power control code (right now: only ARCH_QCOM).
The pwrseq-based PCI pwrctl driver itself will then be selected by the
drivers binding to devices that may require external handling of the
power-up sequence (currently: ath11k and ath12k) based on the value
of HAVE_PWRCTL.
Make all PCI pwrctl Kconfig symbols hidden so that no questions are
asked during configuration.
Fixes: 4565d2652a ("PCI/pwrctl: Add PCI power control core code")
Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Closes: https://lore.kernel.org/lkml/CAHk-=wjWc5dzcj2O1tEgNHY1rnQW63JwtuZi_vAZPqy6wqpoUQ@mail.gmail.com/
Acked-by: Jeff Johnson <quic_jjohnson@quicinc.com> # drivers/net/wireless/ath
Link: https://lore.kernel.org/r/20240717142803.53248-1-brgl@bgdev.pl
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
The majority of the updates here are Dmitry Torokhov's cleanups
for platform code in the pxa and tegra platforms, changing custom
platform_data structures into DT-compatible software node declarations.
The other updates are for the MAINTAINERS file, correcting some
stale or missing entries.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmaVNvgACgkQYKtH/8kJ
UiddAQ//QIfU7YJbB+nLLHURWDZsFqzmdwX9Shwb810TecwkYyeltbjkwYQw6/VD
Pc1C5t08Brnjwgm9Z4jU8dKDeS4znMy1MzjyGoZqYLamNojhChXG4fonhGVYncg4
m3ruXgXZ/xsmqfMloclCtOSB6DWjXk9tVyUDNymXWgATmlwVsZl6saXf5nEo11bu
WKi6kHhfM1s/JKGBaScd/GnxmXpBco4T7ub8cBZ/6Kn5RS6OodSb1ZCiTTI3KHdT
oLzQ+B+MjAF5jlWvrqFuKrosjHB0RiKa/GKlfwsM4ho91Rfm979wsykEacR+iOy6
usbAdfV/AgKT0C6Hd471Kdtpt0mV5lcc4QdwQTAycslHI4CzjRmQW+yHWUJxxOEB
ggEtzKimpVbInN4ygJTnA8dZIawZ/CdCZQ04hQtyEuZamx3MGYVPaNIowNq4CRlv
r6NRgfvQVGeQfpJCOdUySwwxVXDsq+Q8dUvswf6qfDDRyHiAtNqnoNd/G4rsI9Uy
ItsGaFHpaVi1ElAO7IyEb9JzQGRIwxryseET5cUyfhJEM5RFk4aBMYJVFtDgV4H5
KldgfIWpUZyMlM6IxdWziBDvKyrToAXb9NSX7nlcP2879IztNIwW2V+7y4rdX7Mu
fTjLZxkypLdJkKvdcXNwS4toZ+CvpzcjeEJlGcPcVc1JY/Ua3Ck=
=/EgX
-----END PGP SIGNATURE-----
Merge tag 'soc-arm-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull arm SoC platform updates from Arnd Bergmann:
"The majority of the updates here are Dmitry Torokhov's cleanups for
platform code in the pxa and tegra platforms, changing custom
platform_data structures into DT-compatible software node
declarations.
The other updates are for the MAINTAINERS file, correcting some stale
or missing entries"
* tag 'soc-arm-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: pxa: fix build breakage on PXA3xx
ti: omap: MAINTAINERS: move Benoît Cousson to CREDITS
amazon: MAINTAINERS: change to odd fixes and Tsahee Zidenberg to CREDITS
MAINTAINERS: thead: add git tree
ARM: spitz: Use software nodes for the ADS7846 touchscreen
ARM: spitz: Use software nodes to describe LED GPIOs
ARM: spitz: Use software nodes to describe MMC GPIOs
ARM: spitz: Use software nodes to describe LCD GPIOs
ARM: spitz: Use software nodes to describe audio GPIOs
ARM: spitz: Use software nodes to describe SPI CS lines
ARM: spitz: Simplify instantiating SPI controller
ARM: pxa/gumstix: convert vbus gpio to use software nodes
ARM: pxa: consolidate GPIO chip platform data
ARM: spitz: fix GPIO assignment for backlight
ARM: tegra: paz00: Use software nodes to describe GPIOs for WiFi rfkill
MAINTAINERS: ARM: airoha: add entry to cover Airoha SoC
bus: vexpress-config: Add missing MODULE_DESCRIPTION() macro
arm64: layerscape: remove redundant EDAC_SUPPORT selection
dt-bindings: arm: Remove obsolete RTSM DCSCB binding
arm: vexpress: Remove obsolete RTSM DCSCB support
- Core code:
- Interrupt storm detection for the lockup watchdog:
Lockups which are caused by interrupt storms are not easy to debug
because there is no information about the events which make the lockup
detector trigger.
To make this more user friendly, provide an extenstion to interrupt
statistics which allows to take snapshots and an interface to retrieve
the delta to the snapshot. Use this new mechanism in the watchdog code
to do a two stage lockup analysis by taking the snapshot and printing
the deltas for the topmost active interrupts on the second trigger.
Note: This contains both the interrupt and the watchdog changes as
the latter depend on the former obviously.
- Avoid summation loops in the /proc/interrupts output and use the global
counter when possible
- Skip suspended interrupts on CPU hotplug operations to ensure that they
are not delivered before the system resumes the device drivers when
coming out of suspend.
- On CPU hot-unplug interrupts which are affine to the outgoing CPU are
migrated to a different CPU in the affinity mask. This can fail when
the CPUs have no vectors left. Instead of giving up try to migrate it
to any online CPU and thereby breaking the affinity setting in order to
prevent a stale device interrupt which targets an offline CPU
- The usual small cleanups
- Driver code:
- Support for the RISCV AIA MSI controller
- Make the interrupt allocation for the Loongson PCH controller more
flexible to prevent vector exhaustion
- The usual set of cleanups and fixes all over the place
-----BEGIN PGP SIGNATURE-----
iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmZBCM0THHRnbHhAbGlu
dXRyb25peC5kZQAKCRCmGPVMDXSYoeZHEACqMLN3K+1HyWflYtcTHJeYCjZLHS77
2tQeKaaskOA4W6dcGXPxMw5CHqAobHVQQMqgcJxhUdqQiOJnFFnrtCD7JtqM0hWK
UORNbyeovuhAo+iJ0fTuS8p63H7vm2GIWwBLWJnOuChYv/6Yyx5Cald1skvyvbzL
zePhiiAf5mkdmJMeT5wJSCqEWSRYOXsVAJ/0YAwFG3bKkJH3bmDo6SDJY02sXT5P
pjbtD/0hum9wIVT4fNdYleHHQMdBdj9dLlcxXBikHq50mDMw7GxvjKiLcXmoerw3
rEBfVVJp3qpSofpNJZ3HH0ywcF3yUzq04/LPE9Tk2MoQ8NF0GzP8r9Ahke4B7cUj
FysWNiAlC2IisEi6th313FZkTLx0zgewdsdEBTLt8eAE9TU0wamRbo99LZ8i/Qr3
hk7jV8DzL+EDQJLgl4p1iPJgA708eW17tbCxLEa15VKVV6P58miohmhx/IfPO2Gx
FV1PPehtItsmiK/UoRtUCoFdFsqNQtOE+h8DWLyy8RDmhBqGbn9Ut4euXiQIF+rX
WJKPFfslCTR39BrBcZnZeNsgOCN7tEfFRstzjzkey1DaeTGWtxmA5UGhpC2vT74y
YyXluvZlgKr4S64ABmcqQj++hQLho0OQAih3uW5YVxt4VxEUcXYMJOsV1AQGpMjF
UnewWH5opBQdfw==
=jFLf
-----END PGP SIGNATURE-----
Merge tag 'irq-core-2024-05-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull interrupt subsystem updates from Thomas Gleixner:
"Core code:
- Interrupt storm detection for the lockup watchdog:
Lockups which are caused by interrupt storms are not easy to debug
because there is no information about the events which make the
lockup detector trigger.
To make this more user friendly, provide an extenstion to interrupt
statistics which allows to take snapshots and an interface to
retrieve the delta to the snapshot. Use this new mechanism in the
watchdog code to do a two stage lockup analysis by taking the
snapshot and printing the deltas for the topmost active interrupts
on the second trigger.
Note: This contains both the interrupt and the watchdog changes as
the latter depend on the former obviously.
- Avoid summation loops in the /proc/interrupts output and use the
global counter when possible
- Skip suspended interrupts on CPU hotplug operations to ensure that
they are not delivered before the system resumes the device drivers
when coming out of suspend.
- On CPU hot-unplug interrupts which are affine to the outgoing CPU
are migrated to a different CPU in the affinity mask. This can fail
when the CPUs have no vectors left. Instead of giving up try to
migrate it to any online CPU and thereby breaking the affinity
setting in order to prevent a stale device interrupt which targets
an offline CPU
- The usual small cleanups
Driver code:
- Support for the RISCV AIA MSI controller
- Make the interrupt allocation for the Loongson PCH controller more
flexible to prevent vector exhaustion
- The usual set of cleanups and fixes all over the place"
* tag 'irq-core-2024-05-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (51 commits)
irqchip/gic-v3-its: Remove BUG_ON in its_vpe_irq_domain_alloc
cpuidle: Avoid explicit cpumask allocation on stack
irqchip/sifive-plic: Avoid explicit cpumask allocation on stack
irqchip/riscv-aplic-direct: Avoid explicit cpumask allocation on stack
irqchip/loongson-eiointc: Avoid explicit cpumask allocation on stack
irqchip/gic-v3-its: Avoid explicit cpumask allocation on stack
irqchip/irq-bcm6345-l1: Avoid explicit cpumask allocation on stack
cpumask: Introduce cpumask_first_and_and()
irqchip/irq-brcmstb-l2: Avoid saving mask on shutdown
genirq: Reuse irq_is_nmi()
genirq/cpuhotplug: Retry with cpu_online_mask when migration fails
genirq/cpuhotplug: Skip suspended interrupts when restoring affinity
arm64: dts: st: Add interrupt parent to pinctrl on stm32mp251
arm64: dts: st: Add exti1 and exti2 nodes on stm32mp251
ARM: dts: stm32: List exti parent interrupts on stm32mp131
ARM: dts: stm32: List exti parent interrupts on stm32mp151
arm64: Kconfig.platforms: Enable STM32_EXTI for ARCH_STM32
irqchip/stm32-exti: Mark events reserved with RIF configuration check
irqchip/stm32-exti: Skip secure events
irqchip/stm32-exti: Convert driver to standard PM
...
The code changes are fairly minimal, there is a bit of conversion of
the old orion5x platform to modern gpio descriptors, the Kconfig entry
for the added EN7581 platform and a sysfs change for the i.MX PMU
device.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmY+NV8ACgkQYKtH/8kJ
UifY2RAAqvYWec0uzJDgUPuJCh3OL7XnpV8UvdUdc9IK4JBbXl/KPRj0m3qY1c+G
uhRJ9lDYsEUd0bs3KI/qSSZ2sFmkO4TxpBEbaENCRSolW1hRWzO6a9Opiqfvyvnq
5u1hBJ2QNuVovfcAtdLkS63mafIn5m+RzuQELwcbSllCxWlfUJDnOF1ABDr6JhZ2
YF7bzdJCpTP6NGUuiG0fOk9/k573Y4xJw99h/B2+qSNA/MQrVwEZ6AcVGogRsYf+
ySpFX7itMqUCne77ULKUdP3T29+H+0y3oBln+5lxeqKpDrFBLXov5+JhRpUuhYza
FNwbf9FzGpO1hTpO/pXj+IjvUj9CLn9FB/papTSh+Hnm4VNWfYEU3AG4yUlhDIdt
8ANZKL9hw4kevYFTUpP4aG/5sRu4iFLdXtMUaASSJrr9D+UH0ZEs28rqpSdnKb7D
UMi7r9/yXHxIpSqLbB7RntyRZdD0Nmq78TvKRYIzZSfVb0L48YEInYS32RC1BvKY
kNL5F48QHHqCktA144QaR1t0m1YAx35BignTGDZ7oL5qMvlcQvbDKL/3BzqEfqBt
CnGrsErOsTrH4/jdlTn7EMrtHag/ksJqbWkh/09kQZYyaQUOpm/1SL6Pgdb/7RqN
1jmlBAZrKFDEccjetMFnXIhaxuWOR1saWrjLgTuwctZKfEUBdmk=
=zzwg
-----END PGP SIGNATURE-----
Merge tag 'soc-arm-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC code changes from Arnd Bergmann:
"The code changes are fairly minimal, there is a bit of conversion of
the old orion5x platform to modern gpio descriptors, the Kconfig entry
for the added EN7581 platform and a sysfs change for the i.MX PMU
device"
* tag 'soc-arm-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
arm64: add Airoha EN7581 platform
ARM: orion5x: Convert TS409 board to GPIO descriptors for LEDs
ARM: orion5x: Convert Net2big board to GPIO descriptors for LEDs
ARM: orion5x: Convert MV2120 board to GPIO descriptors for LEDs
ARM: orion5x: Convert DNS323 board to GPIO descriptors for LEDs
ARM: orion5x: Convert D2Net board to GPIO descriptors for LEDs
ARM: imx: Assign parents for mmdc event_source devices
Introduce the Kconfig entry for the Airoha EN7581 multicore architecture
available in the Airoha EN7581 evaluation board.
Signed-off-by: Daniel Danzberger <dd@embedd.com>
Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/d52d95db313e6a58ba997ba2181faf78a1014bcc.1709975956.git.lorenzo@kernel.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Introduce a STM32 firewall framework that offers to firewall consumers
different firewall services such as the ability to check their access
rights against their firewall controller(s).
The STM32 firewall framework offers a generic API for STM32 firewall
controllers that is defined in their drivers to best fit the
specificity of each firewall.
There are various types of firewalls:
-Peripheral firewalls that filter accesses to peripherals
-Memory firewalls that filter accesses to memories or memory regions
-No type for undefined type of firewall
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Highlights:
----------
STM32MP25 family is composed of 4 SoCs defined as following:
-STM32MP251: common part composed of 1*Cortex-A35,
common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3,
parallel and DSI display, 1*ETH ...
-STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH,
CAN-FD and LVDS display.
-STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
-STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).
A second diversity layer exists for security features/A35 frequency:
-STM32MP25xY, "Y" gives information:
-Y = A means A35@1.2GHz + no cryp IP and no secure boot.
-Y = C means A35@1.2GHz + cryp IP and secure boot.
-Y = D means A35@1.5GHz + no cryp IP and no secure boot.
-Y = F means A35@1.5GHz + cryp IP and secure boot.
This PR adds the STM32MP257F EV1 board support. This board embeds a
STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports),
2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
-----BEGIN PGP SIGNATURE-----
iQJQBAABCgA7FiEEctl9+nxzUSUqdELdf5rJavIecIUFAmSG5+AdHGFsZXhhbmRy
ZS50b3JndWVAZm9zcy5zdC5jb20ACgkQf5rJavIecIUXEA/4mb17fH6BUDc1wGHb
kl7XJh8s9A98Wbjlei+fgZ6VfDRU1KuEkna/TJ+8QwBadb450RSPxCozWyaT94kq
EeVHw2pyQELBA7T4Cu/3OzyD2dQj/hELbWKlUT5UedMibguxYb+IyxMqOrw29Ghb
t5G1cfJknkbXQDKrEVDynUHoRcDIb3vLXhvL3Z8ExSDBaaVdhrpXyJow4fRBUgtY
gqEnVJHOVHsu5k+Ah2/2SaMUpxfQIUduxFMsk7pAFiZU+nRQI03Cn6EKADCIgmS0
1LZVhjfO15Tm5X2bDN+gHqC+3ASZGZqe4KkUF5RfIN+2K1Jo8CMCoezHga0y03Lb
EN6PEoHhriqNs/2azFLTQbua0RzkdJxXNNWAG5I+I0qim6hicTV9YCkkxIQlhNxu
K67BdvBEJrDNBYlkk4DDaiGRuPFSoitwYMnZqCrvLGtxtTbjrMjppCCvdJPrCGBr
aY/1hLePnnxdBvCFKODKkiAT48gPjZoEhLrbegIY2XMqseciX4o9JZbXmnMVdpqD
2l1M2xsyVe5Jxv8JRfnr6GfUj0FVIgxB8tUII7OpXxTGZN9MaOt/92DKTbvLdvma
MwIOIMKB5QYFytCNwjFMI2LJopfiFJNUKk2Yd+WNWGaEG1LmdhTSIIROQBMDM5Zg
xTR+DvbdtbgyTSSsuBDGw1UWnA==
=WkNC
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSSC/wACgkQYKtH/8kJ
UidpWhAAn9bQwdIJdetMmMiJuvFJIqPg48K9OmvEpEYCxAwVFuKTV+ddGDM2kLwB
rinJ5R92FsCUBN54mPpfq75atuhZA8S3Od4N8jbjK7Geqq0MIUv6yaGYNyKJfDrx
NO3+UzIpF17eqiXDTY4ZEdw+FfWJ1fr1rKN2DNyqIQDIibvOR8smuAE9suIdNsht
0k0LOCk+PXRaNws6wIeXM71v42trb8S5UG02qQzet1qwsK7OXUc7xouTr6vQ7xMR
H4NiuEL0XfkhsxsSLhbFSpWzRoVcKhhyZzibNu4l5npBvL0VZPyYrJOU7MAODy5D
IWIS07/BNWrKx/XhCyz7w0ID2SsMGxAgGeOMx1eG3WT5953z5tWOqBgZGWrObQMO
QR4F2h+f9InLblHEdLa+n1Nfm6SAgGEA+JnDDHSbuiH1t/g01wazxCAi6Awoxur6
jv7iINiy2UauRs7/Fns0z1J0gag/8afxTYiEzBQSMdrE4zgaKKGtryoflUOXZe9W
foXtU4+mRAExrZN/3gxYQyvvLxQF7vllCYtuzeUyJzpXuYwE5clpjjEn93txXtPr
EjIS+fg3cgABaD26607ueGomQIdKxjWj/1tZSaut1yWs/zeuRjS15dT68IzzI0mK
Qk1v6mLx+gdnOQv8mn5JfzOC8MTDBrAE53B6M+mI9nZrV3VhhhE=
=fxHg
-----END PGP SIGNATURE-----
Merge tag 'stm32-mp25-for-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/newsoc
STM32 STM32MP25 for v6.5, round 1
Highlights:
----------
STM32MP25 family is composed of 4 SoCs defined as following:
-STM32MP251: common part composed of 1*Cortex-A35,
common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3,
parallel and DSI display, 1*ETH ...
-STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH,
CAN-FD and LVDS display.
-STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
-STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).
A second diversity layer exists for security features/A35 frequency:
-STM32MP25xY, "Y" gives information:
-Y = A means A35@1.2GHz + no cryp IP and no secure boot.
-Y = C means A35@1.2GHz + cryp IP and secure boot.
-Y = D means A35@1.5GHz + no cryp IP and no secure boot.
-Y = F means A35@1.5GHz + cryp IP and secure boot.
This PR adds the STM32MP257F EV1 board support. This board embeds a
STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports),
2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
* tag 'stm32-mp25-for-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (44 commits)
MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE
arm64: defconfig: enable ARCH_STM32 and STM32 serial driver
arm64: dts: st: add stm32mp257f-ev1 board support
dt-bindings: stm32: document stm32mp257f-ev1 board
arm64: dts: st: introduce stm32mp25 pinctrl files
arm64: dts: st: introduce stm32mp25 SoCs family
arm64: introduce STM32 family on Armv8 architecture
dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon
pinctrl: stm32: add stm32mp257 pinctrl support
dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages
ARM: dts: stm32: fix i2s endpoint format property for stm32mp15xx-dkx
ARM: dts: stm32: Fix audio routing on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: add required supplies of ov5640 in stm32mp157c-ev1
ARM: dts: stm32: Update to generic ADC channel binding on DHSOM systems
ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-testbench
ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-drc
ARM: dts: stm32: adopt generic iio bindings for adc channels on emstamp-argon
ARM: dts: stm32: adopt generic iio bindings for adc channels on stm32mp157c-ed1
ARM: dts: stm32: enable adc on stm32mp15xx-dkx boards
ARM: dts: stm32: add vrefint support to adc2 on stm32mp15
...
Link: https://lore.kernel.org/r/080fc303-45c1-6cc0-4c5e-694e730896a6@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add a dedicated ARCH_STM32 for STM32 SoCs config. First STM32 Armv8 SoC
family is the STM32MP25 which is composed of STM32MP251, STM32MP253,
STM32MP255, STM32MP257 SoCs.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
- Support for arm64 SME 2 and 2.1. SME2 introduces a new 512-bit
architectural register (ZT0, for the look-up table feature) that Linux
needs to save/restore.
- Include TPIDR2 in the signal context and add the corresponding
kselftests.
- Perf updates: Arm SPEv1.2 support, HiSilicon uncore PMU updates, ACPI
support to the Marvell DDR and TAD PMU drivers, reset DTM_PMU_CONFIG
(ARM CMN) at probe time.
- Support for DYNAMIC_FTRACE_WITH_CALL_OPS on arm64.
- Permit EFI boot with MMU and caches on. Instead of cleaning the entire
loaded kernel image to the PoC and disabling the MMU and caches before
branching to the kernel bare metal entry point, leave the MMU and
caches enabled and rely on EFI's cacheable 1:1 mapping of all of
system RAM to populate the initial page tables.
- Expose the AArch32 (compat) ELF_HWCAP features to user in an arm64
kernel (the arm32 kernel only defines the values).
- Harden the arm64 shadow call stack pointer handling: stash the shadow
stack pointer in the task struct on interrupt, load it directly from
this structure.
- Signal handling cleanups to remove redundant validation of size
information and avoid reading the same data from userspace twice.
- Refactor the hwcap macros to make use of the automatically generated
ID registers. It should make new hwcaps writing less error prone.
- Further arm64 sysreg conversion and some fixes.
- arm64 kselftest fixes and improvements.
- Pointer authentication cleanups: don't sign leaf functions, unify
asm-arch manipulation.
- Pseudo-NMI code generation optimisations.
- Minor fixes for SME and TPIDR2 handling.
- Miscellaneous updates: ARCH_FORCE_MAX_ORDER is now selectable, replace
strtobool() to kstrtobool() in the cpufeature.c code, apply dynamic
shadow call stack in two passes, intercept pfn changes in set_pte_at()
without the required break-before-make sequence, attempt to dump all
instructions on unhandled kernel faults.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAmP0/QsACgkQa9axLQDI
XvG+gA/+JDVEH9wRzAIZvbp9hSuohPc48xgAmIMP1eiVB0/5qeRjYAJwS33H0rXS
BPC2kj9IBy/eQeM9ICg0nFd0zYznSVacITqe6NrqeJ1F+ftS4rrHdfxd+J7kIoCs
V2L8e+BJvmHdhmNV2qMAgJdGlfxfQBA7fv2cy52HKYcouoOh1AUVR/x+yXVXAsCd
qJP3+dlUKccgm/oc5unEC1eZ49u8O+EoasqOyfG6K5udMgzhEX3K6imT9J3hw0WT
UjstYkx5uGS/prUrRCQAX96VCHoZmzEDKtQuHkHvQXEYXsYPF3ldbR2CziNJnHe7
QfSkjJlt8HAtExA+BkwEe9i0MQO/2VF5qsa2e4fA6l7uqGu3LOtS/jJd23C9n9fR
Id8aBMeN6S8+MjqRA9L2uf4t6e4ISEHoG9ZRdc4WOwloxEEiJoIeun+7bHdOSZLj
AFdHFCz4NXiiwC0UP0xPDI2YeCLqt5np7HmnrUqwzRpVO8UUagiJD8TIpcBSjBN9
J68eidenHUW7/SlIeaMKE2lmo8AUEAJs9AorDSugF19/ThJcQdx7vT2UAZjeVB3j
1dbbwajnlDOk/w8PQC4thFp5/MDlfst0htS3WRwa+vgkweE2EAdTU4hUZ8qEP7FQ
smhYtlT1xUSTYDTqoaG/U2OWR6/UU79wP0jgcOsHXTuyYrtPI/Q=
=VmXL
-----END PGP SIGNATURE-----
Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Catalin Marinas:
- Support for arm64 SME 2 and 2.1. SME2 introduces a new 512-bit
architectural register (ZT0, for the look-up table feature) that
Linux needs to save/restore
- Include TPIDR2 in the signal context and add the corresponding
kselftests
- Perf updates: Arm SPEv1.2 support, HiSilicon uncore PMU updates, ACPI
support to the Marvell DDR and TAD PMU drivers, reset DTM_PMU_CONFIG
(ARM CMN) at probe time
- Support for DYNAMIC_FTRACE_WITH_CALL_OPS on arm64
- Permit EFI boot with MMU and caches on. Instead of cleaning the
entire loaded kernel image to the PoC and disabling the MMU and
caches before branching to the kernel bare metal entry point, leave
the MMU and caches enabled and rely on EFI's cacheable 1:1 mapping of
all of system RAM to populate the initial page tables
- Expose the AArch32 (compat) ELF_HWCAP features to user in an arm64
kernel (the arm32 kernel only defines the values)
- Harden the arm64 shadow call stack pointer handling: stash the shadow
stack pointer in the task struct on interrupt, load it directly from
this structure
- Signal handling cleanups to remove redundant validation of size
information and avoid reading the same data from userspace twice
- Refactor the hwcap macros to make use of the automatically generated
ID registers. It should make new hwcaps writing less error prone
- Further arm64 sysreg conversion and some fixes
- arm64 kselftest fixes and improvements
- Pointer authentication cleanups: don't sign leaf functions, unify
asm-arch manipulation
- Pseudo-NMI code generation optimisations
- Minor fixes for SME and TPIDR2 handling
- Miscellaneous updates: ARCH_FORCE_MAX_ORDER is now selectable,
replace strtobool() to kstrtobool() in the cpufeature.c code, apply
dynamic shadow call stack in two passes, intercept pfn changes in
set_pte_at() without the required break-before-make sequence, attempt
to dump all instructions on unhandled kernel faults
* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (130 commits)
arm64: fix .idmap.text assertion for large kernels
kselftest/arm64: Don't require FA64 for streaming SVE+ZA tests
kselftest/arm64: Copy whole EXTRA context
arm64: kprobes: Drop ID map text from kprobes blacklist
perf: arm_spe: Print the version of SPE detected
perf: arm_spe: Add support for SPEv1.2 inverted event filtering
perf: Add perf_event_attr::config3
arm64/sme: Fix __finalise_el2 SMEver check
drivers/perf: fsl_imx8_ddr_perf: Remove set-but-not-used variable
arm64/signal: Only read new data when parsing the ZT context
arm64/signal: Only read new data when parsing the ZA context
arm64/signal: Only read new data when parsing the SVE context
arm64/signal: Avoid rereading context frame sizes
arm64/signal: Make interface for restore_fpsimd_context() consistent
arm64/signal: Remove redundant size validation from parse_user_sigframe()
arm64/signal: Don't redundantly verify FPSIMD magic
arm64/cpufeature: Use helper macros to specify hwcaps
arm64/cpufeature: Always use symbolic name for feature value in hwcaps
arm64/sysreg: Initial unsigned annotations for ID registers
arm64/sysreg: Initial annotation of signed ID registers
...
All these platforms are ARMv8 or newer and choosing the platforms in
menuconfig is much easier if the titles start with something specific.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230120125722.270722-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Do not automatically select the GPIOLIB and PINCTRL config options as
they are already automatically selected as part of the SOC_RENESAS
config option in drivers/soc/renesas/Kconfig.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20221027112459.77413-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The main changes this time are for the organization of the Kconfig
files, introducing per-vendor top-level options on arm64 to match
those on arm32, and making the platform selection on arm32 more
uniform, in particular for the remaining StrongARM platforms that
still have a couple of special cases compared to the more recent
ones.
I also did a cleanup of the old Footbridge platform, which was
the last holdout for the phys_to_dma()/dma_to_phys() interface
that is now completely gone from arm32, completing work started
by Christoph Hellwig.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmM+n3EACgkQmmx57+YA
GNlnjA/+JR/0Y8gzRw6lGLB254R1zLqKzoZC065+zk++qN/t9pIEAvICaTO7ooIY
Iz79crIyQ7aJptVfDyb44hrC23sBsY/ujkh7WmfLDAs7Jf9a1xOgcQONz6uOk+3p
qsCXEjyn6O4EPtCBxiICA7vcVUAeM+wkcuV2KQnW9b4CNlLXdhyn1ijwnGO4Zm6g
h2w0gX2TVkoR2ZSqWh5CCk9OOfgQRrHGMHzX0iRXtYApJk/zA8ywnuRsqts8R3lu
04Jl17szmMoeN2RQjf/gTJc7xpWvs7SzfyNTXXoXmB7x9c27eQXyoUpWC9o/BPPb
YNqv2Xmm0+cMsmPvkY/7poDlPMObh9exV2dDQ3XKoyoVPu+hBL4AsXMchQ7rsrVk
+FvdTxZTpl42sx9KitRQG/7WZ1pmxBBcFVB4fmVJcCF4OcOpXH7i1VmsB6PAOaIF
CKUpaIjnTZ1VbqhADqCzRfUSI4HiAHuo886rAYcCK3K47UpLjBwcwOTyXZccG0SL
z9IQkm53DgsJVLEUmtwAfVF57SciWxmQZid7vM2xQX/03pwO2/x4d347EcJJZcHS
vuqWZD0Wp3VBuj2fLFk83WaaQJzP5rzJAewKbR4KyxraMyTvOEYVBa18AMnZQ6sw
aFecU9YXa8PhgaiFrfepZcTby0Bm+YSc8ko80se44zz07kZW/y8=
=xsKV
-----END PGP SIGNATURE-----
Merge tag 'arm-soc-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC updates from Arnd Bergmann:
"The main changes this time are for the organization of the Kconfig
files, introducing per-vendor top-level options on arm64 to match
those on arm32, and making the platform selection on arm32 more
uniform, in particular for the remaining StrongARM platforms that
still have a couple of special cases compared to the more recent ones.
I also did a cleanup of the old Footbridge platform, which was the
last holdout for the phys_to_dma()/dma_to_phys() interface that is now
completely gone from arm32, completing work started by Christoph
Hellwig"
* tag 'arm-soc-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (21 commits)
ARM: aspeed: Kconfig: Fix indentation
ARM: Drop CMDLINE_* dependency on ATAGS
ARM: Drop CMDLINE_FORCE dependency on !ARCH_MULTIPLATFORM
ARM: s3c: remove orphan declarations from arch/arm/mach-s3c/devs.h
pxa: Drop if with an always false condition
ARM: orion: fix include path
ARM: shmobile: Drop selecting SOC_BUS
arm64: renesas: Drop selecting SOC_BUS
ARM: disallow PCI with MMU=n again
ARM: footbridge: remove custom DMA address handling
MAINTAINERS: Add BCM4908 maintainer to BCMBCA entry
ARM: footbridge: move isa-dma support into footbridge
ARM: footbridge: remove leftover from personal-server
ARM: footbridge: remove addin mode
arm64: Kconfig.platforms: Group NXP platforms together
arm64: Kconfig.platforms: Re-organized Broadcom menu
ARM: make ARCH_MULTIPLATFORM user-visible
ARM: fix XIP_KERNEL dependencies
ARM: Kconfig: clean up platform selection
ARM: simplify machdirs/platdirs handling
...
Don't automatically select the SOC_BUS config option as we already have
automatically selected it as part of the SOC_RENESAS config option [0]
as renesas-soc.c [1] uses the APIs provided by SOC_BUS config option.
[0] drivers/soc/renesas/Kconfig
[1] drivers/soc/renesas/renesas-soc.c
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220915233640.415305-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Group the three NXP platforms under an ARCH_NXP menuconfig symbol to
make make selection of similar vendor SoCs visually nicer.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20220829173830.3567047-3-f.fainelli@gmail.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
There are now multiple Broadcom SoCs supported so group them under their
own menu such that the selection is visually more appealing and we can
easily add new platforms there in the future. This allows us to move
ARCH_BRCMSTB back to its siblings.
No functional changes introduced.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20220829173830.3567047-2-f.fainelli@gmail.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Delete ARCH_BCM4908 platform Kconfig for BCM4908 SoC as it is replaced
by ARCH_BCMBCA and move its selection to ARCH_BCMBCA.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/20220803175455.47638-8-william.zhang@broadcom.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This adds initial support for two SoC families that have been under
review for a while. In both cases, the origonal idea was to have a
minimally functional version, but we ended up leaving out the clk drivers
that are still under review and will be merged through the corresponding
subsystem tree.
The Nuvoton NPCM8xx is a 64-bit Baseboard Management Controller and
based on the 32-bit NPCM7xx family but is now getting added to
arch/arm64 as well.
Sunplus SP7021, also known as Plus1, is a general-purpose
System-in-Package design based on the 32-bit Cortex-A7 SoC
on the main chip, plus an I/O chip and memory in the same
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLo+24ACgkQmmx57+YA
GNkPVw//XAC/uK7WR4oz1D1YaPPNhEvFa6hV1gjGB7Iif72SzyDJmC+36MATU/AY
neQjCOLJMhxI0hpDGY9nLYe+aP1C6vD32zsjffjt/+s9em+YZZCUkRJuQ5xO3fID
Uk8ZAnCIcOqX9sjXr9ChW8irlcWFbKzhgWXnPqwQmycIaE7QVz1wx32dbc64YuAK
S+290U8wbj8bukr33TyZPMdYlfqNU3c1W+dCaeVsQlX1juoHEV3stmIjslRefd6X
Jre22YJE41VlPufZej76nHXuVnjKf54Oi347TcbPOWNDtEAIESt3mzKy+zICBT2p
v01rNBf0SogyOtSbWDPTFCAH9W9hujSOJIUOWpbOLaPdfElXxcoTBwj2e2LMoW0k
ke7YR1m6FKDam5GFU9Oe98CWIiVm/GnTA5mnhhETU1QTXQ3KeZ+Z8X779YuSWPv9
kJuOPRSk9NdcfRtxZz1vpCvhv/2hBbeBuz+GZi3bisMWdvVqS3lFqVbr6kziQbJZ
kE6KJH48FdL0VLVvuy+aNSF2umLT42b+5+cmQFuP2zePQgo1DEMKEtFXpZjQJbha
3iu3sHnieOFMLcbNzbqSz2im3yYNBjl1M5qoGEXaw3Rkzqiht0kMNvAa4LmAejbh
E+5BIczwWNbaUKgToV1ij65O4a78Bw98m2SIS7awEZC5MW/nXYA=
=7Id+
-----END PGP SIGNATURE-----
Merge tag 'arm-newsoc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM new SoC support from Arnd Bergmann:
"This adds initial support for two SoC families that have been under
review for a while. In both cases, the origonal idea was to have a
minimally functional version, but we ended up leaving out the clk
drivers that are still under review and will be merged through the
corresponding subsystem tree.
The Nuvoton NPCM8xx is a 64-bit Baseboard Management Controller and
based on the 32-bit NPCM7xx family but is now getting added to
arch/arm64 as well.
Sunplus SP7021, also known as Plus1, is a general-purpose
System-in-Package design based on the 32-bit Cortex-A7 SoC on the main
chip, plus an I/O chip and memory in the same"
* tag 'arm-newsoc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
MAINTAINERS: rectify entry for ARM/NUVOTON NPCM ARCHITECTURE
arm64: defconfig: Add Nuvoton NPCM family support
arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
arm64: dts: nuvoton: Add initial NPCM8XX device tree
arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
dt-bindings: arm: npcm: Add maintainer
reset: npcm: Add NPCM8XX support
dt-bindings: reset: npcm: Add support for NPCM8XX
reset: npcm: using syscon instead of device data
ARM: dts: nuvoton: add reset syscon property
dt-bindings: reset: npcm: add GCR syscon property
dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
dt-bindings: watchdog: npcm: Add npcm845 compatible string
dt-bindings: timer: npcm: Add npcm845 compatible string
ARM: dts: Add Sunplus SP7021-Demo-V3 board device tree
ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig
ARM: sunplus: Add initial support for Sunplus SP7021 SoC
irqchip: Add Sunplus SP7021 interrupt controller driver
...
This adds support for the Nuvoton NPCM8XX Board Management
controller (BMC) SoC family.
The NPCM8XX based quad-core Cortex-A35 ARMv8 architecture.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
