Rockchip SoC TRM, SoC datasheet and board schematics always refer to
the same gpio numbers - even if not all are used for a specific board.
In order to not have to re-define them for every board add the
aliases to SoC dtsi files.
Co-developed-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/89f2a229-9f14-d43f-c53d-5d4688e70456@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
SoC TRM, SoC datasheet and board schematics always refer to the
same uart numbers - even if not all are used for a specific board.
In order to not have to re-define them for every board move the
aliases to SoC dtsi for RK3128 like it's being done for all other
Rockchip ARM SoCs.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20231202130506.66738-5-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
SoC TRM, SoC datasheet and board schematics always refer to the
same i2c numbers - even if not all are used for a specific board.
In order to not have to re-define them for every board move the
aliases to SoC dtsi for RK3128 like it's being done for all other
Rockchip ARM SoCs.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20231202130506.66738-4-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
SoC TRM, SoC datasheet and board schematics always refer to the
same gpio numbers - even if not all are used for a specific board.
In order to not have to re-define them for every board move the
aliases to SoC dtsi for RK3128 like it's being done for most other
Rockchip ARM SoCs.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20231202130506.66738-3-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Sonoff iHost is gateway device designed to provide a Smart Home Hub,
it is based on Rockchip RV1126. There is also a version with 2GB RAM
based off the RV1109 dual core SoC.
Features:
- Rockchip RV1126
- 4GB DDR4
- 8GB eMMC
- microSD slot
- RMII Ethernet PHY
- 1x USB 2.0 Host
- 1x USB 2.0 OTG
- Realtek RTL8723DS WiFi/BT
- EFR32MG21 Silabs Zigbee radio
- Speaker/Microphone
This patch adds the initial device tree for this device, it is largely
based off the device trees for mainline Edgeble Neu2 and downstream
Rockchip rv1126-evb-v13 configs. It has been adapted with relevant
peripheral and GPIO pins for the iHost.
Signed-off-by: Tim Lunn <tim@feathertop.org>
Link: https://lore.kernel.org/r/20231203124004.2676174-8-tim@feathertop.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Rockchip rv1109 SoC is a dual core version of the rv1126. It is
otherwise identical and shares the same device tree config.
This patch introduces a dtsi file to drop the additional cpu nodes.
Taken from Rockchip BSP kernel.
Signed-off-by: Tim Lunn <tim@feathertop.org>
Link: https://lore.kernel.org/r/20231203124004.2676174-7-tim@feathertop.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add uart3m2_xfer and uart4m2_xfer pins for Rockchip RV1126. These are
used as serial ports for the indicator and Zigbee radio on the iHost.
Signed-off-by: Tim Lunn <tim@feathertop.org>
Link: https://lore.kernel.org/r/20231203124004.2676174-2-tim@feathertop.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
RK3128 SoCs have Mali400 MP2 GPU.
Add the respective device tree node and the correspondending opp-table.
The frequencies and voltages of the opp-table have been taken from
downstream kernel.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20231204153547.97877-3-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Without setting the parent for SCLK_USB480M the clock will use xin24m as
it's default parent.
While this is generally not an issue for the usb blocks to work, it becomes
an issue for RK3128 since SCLK_USB480M can be a parent for other HW blocks
(GPU, VPU, VIO), but they will never chose it, since it is currently always
running at OSC frequency which is to slow for their needs.
This sets the usb2 phy's output as SCLK_USB480M's parent and it's users
can chose it if desired.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20231119121340.109025-6-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The driver currently won't probe correctly if those values are missing.
They have been taken from dowstream kernel and match those of other
Rockchip SoCs.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20231119121340.109025-5-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
There are a couple new SoCs that are supported for the first time:
- AMD Pensando Elba is a data processing unit based on Cortex-A72
CPU cores
- Sophgo makes RISC-V based chips, and we now support the CV1800B
chip used in the milkv-duo board and the massive sg2042 chip in the
milkv-pioneer, a 64-core developer workstation.
- Qualcomm Snapdragon 720G (sm7125) is a close relative of
Snapdragon 7c and gets added with some Xiaomi phones
- Renesas gains support for the R8A779F4 (R-Car S4-8) automotive
SoC and the RZ/G3S (R9A08G045) embedded SoC.
There are also a bunch of newly supported machines that use
already supported chips. On the 32-bit side, we have:
- USRobotics USR8200 is a NAS/Firewall/router based on the ancient
Intel IXP4xx platform
- A couple of machines based on the NXP i.MX5 and i.MX6 platforms
- One machine each for Allwinner V3s, Aspeed AST2600, Microchip
sama5d29 and ST STM32mp157
The other ones all use arm64 cores on chips from allwinner,
amlogic, freescale, mediatek, qualcomm and rockchip.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmVC3jwACgkQYKtH/8kJ
Uic3Jg//UgKUEr6ckxInnDew/yHW5AOQ35NKWCLNDysZZVnnnWY44j98Sw++NXyY
WX9rdQBYWf6XZaIynCIF0RqkYSsuPw5jmEIy5PH/JwFkwEvUgv/FFd285MdHa/zR
Rw61K+Aqy/qUDzpEz75z+uy3A0DX6N3ZYP0qvKxzT+oKSkOVYz3rPN5VcMYuPCxO
SpXZMz4CPjBf4RCQeApo80JO3SIW0Mnx1Fu589fJrlWhqmlSer7WlmSA3OMcBmKC
5WgNljieEQidYIhlmZDLnDIL7ot2g+0ESz8nYky3UFRKR3MFDyi4yA7PJrr/EMsK
X7u8eEESrAqjpVJJKgo+q3foV1nYSaGt9vU/mxaiwme44mzhZLo/xfuzpylZRorW
9ny3bP5GaiReWog15sCzwM3D/H+eJbtDKKiU7QasmXjtl+k8i6hAtvuISVeYkPae
n+SdMh3rNsP8n71ybD6aKLp41bQbiO4iUgkyYLh7NHsuSLKq/+EKTiyYmXB6egAZ
eeN+JEKvFgwROHCt39UA0Fo+PbOmeOHbNywLMrr1hZPT3ytroe/rgJEt+qdrCzN7
JcKcNTSy2sQX/GIKQ5qHHmphWZsD38SoqsiPtfsrprZiMXwbER23vnFXh7CHGL4I
gAra/iNHSsHl5FrF43qhyZA9vCNDYvo13LbS/kyDZ7tO9Q+8M/Q=
=NnPm
-----END PGP SIGNATURE-----
Merge tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC DT updates from Arnd Bergmann:
"There are a couple new SoCs that are supported for the first time:
- AMD Pensando Elba is a data processing unit based on Cortex-A72 CPU
cores
- Sophgo makes RISC-V based chips, and we now support the CV1800B
chip used in the milkv-duo board and the massive sg2042 chip in the
milkv-pioneer, a 64-core developer workstation.
- Qualcomm Snapdragon 720G (sm7125) is a close relative of Snapdragon
7c and gets added with some Xiaomi phones
- Renesas gains support for the R8A779F4 (R-Car S4-8) automotive SoC
and the RZ/G3S (R9A08G045) embedded SoC.
There are also a bunch of newly supported machines that use already
supported chips. On the 32-bit side, we have:
- USRobotics USR8200 is a NAS/Firewall/router based on the ancient
Intel IXP4xx platform
- A couple of machines based on the NXP i.MX5 and i.MX6 platforms
- One machine each for Allwinner V3s, Aspeed AST2600, Microchip
sama5d29 and ST STM32mp157
The other ones all use arm64 cores on chips from allwinner, amlogic,
freescale, mediatek, qualcomm and rockchip"
* tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (641 commits)
ARM: dts: BCM5301X: Set switch ports for Linksys EA9200
ARM: dts: BCM5301X: Set fixed-link for extra Netgear R8000 CPU ports
ARM: dts: BCM5301X: Explicitly disable unused switch CPU ports
ARM: dts: BCM5301X: Relicense Vivek's code to the GPL 2.0+ / MIT
ARM: dts: BCM5301X: Relicense Felix's code to the GPL 2.0+ / MIT
ARM: dts: BCM5301X: Set MAC address for Asus RT-AC87U
arm64: dts: socionext: add missing cache properties
riscv: dts: thead: convert isa detection to new properties
arm64: dts: Update cache properties for socionext
arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
arm64: dts: ti: k3-am654-icssg2: add ICSSG2 Ethernet support
arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes
arm64: dts: ti: k3-am62p5-sk: Updates for SK EVM
arm64: dts: ti: k3-am62p: Add nodes for more IPs
arm64: dts: rockchip: Add Turing RK1 SoM support
dt-bindings: arm: rockchip: Add Turing RK1
dt-bindings: vendor-prefixes: add turing
arm64: dts: rockchip: Add DFI to rk3588s
arm64: dts: rockchip: Add DFI to rk356x
arm64: dts: rockchip: Always enable DFI on rk3399
...
This will allow frequency-scaling for the cpu-cores.
Operating frequencies and voltages have been taken from Rockchip's
downstream kernel.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829214004.314932-10-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
For bring-up of the non-boot cpu cores the enable-method for RK3036 can be
re-used.
This adds a (small) chunk of SRAM for execution of the SMP trampoline code
and the respective enable-method property to the cpus.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829214004.314932-8-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
In order to support bring-up of the non-boot cores, this patch adds the
reset controls for the cpu cores.
They are required/will be used by the Rockchip platsmp driver.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829214004.314932-6-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Currently the Rockchip timer source clocks are set to xin24 for no obvious
reason and the actual timer clocks (SCLK_TIMER*) will get disabled during
boot process as they have no user. That will make the SoC stuck as no timer
source exists.
Fixes: a0201bff62 ("ARM: dts: rockchip: add rk3128 soc dtsi")
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829203721.281455-12-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Like most other Rockchip ARM SoCs, the PL330 needs the
arm,pl330-periph-burst quirk in order to work as expected.
Add it.
Fixes: a0201bff62 ("ARM: dts: rockchip: add rk3128 soc dtsi")
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829203721.281455-10-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
RV1126 VOP_LITE supports the video output processing ofMIPI DSI,
RGB display interfaces with max output resolution of 1920x1080.
Add support for vop in rv1126.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20230731110012.2913742-11-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Main supply volatge for Edgeble Neu2 IO board is 12V DC.
Add the 12v supply regulator for it and input to vcc5v0_sys.
Since the power regulator is part of IO board circuit, move the
regulator in IO dts file.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20230731103518.2906147-14-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
EMMC_RSTN GPIO1_A3 is connected to FSPI_CLK in Edgeble Neu2
board.
So, drop the same GPIO pin from eMMC.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20230731103518.2906147-11-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The arm dts directory has grown to 1559 boards which makes it a bit
unwieldy to maintain and use. Past attempts stalled out due to plans to
move .dts files out of the kernel tree. Doing that is no longer planned
(any time soon at least), so let's go ahead and group .dts files by
vendors. This move aligns arm with arm64 .dts file structure.
There's no change to dtbs_install as the flat structure is maintained on
install.
The naming of vendor directories is roughly in this order of preference:
- Matching original and current SoC vendor prefix/name (e.g. ti, qcom)
- Current vendor prefix/name if still actively sold (SoCs which have
been aquired) (e.g. nxp/imx)
- Existing platform name for older platforms not sold/maintained by any
company (e.g. gemini, nspire)
The whole move was scripted with the exception of MAINTAINERS and a few
makefile fixups.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Paul Barker <paul.barker@sancloud.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Nick Hawkins <nick.hawkins@hpe.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Peter Rosin <peda@axentia.se>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Romain Perier <romain.perier@gmail.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
