Commit Graph

7 Commits

Author SHA1 Message Date
Pierre-Henry Moussay
d6d0af1b9e
dt-bindings: spi: add PIC64GX SPI/QSPI compatibility to MPFS SPI/QSPI bindings
PIC64GX SPI/QSPI are compatible with MPFS SPI/QSPI driver, we just use
fallback mechanism

Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Link: https://patch.msgid.link/20240725121609.13101-5-pierre-henry.moussay@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-08-14 18:26:52 +01:00
Prajna Rajendra Kumar
3b4c0fbc19 spi: dt-bindings: Add num-cs property for mpfs-spi
The PolarFire SoC SPI "hard" controller supports eight CS lines, out of
which only one CS line is physically wired. The default value of
'num-cs' was never set and it did not didn't impose a maximum value.

To reflect this hardware limitation in the device tree, the binding
enforces that the 'num-cs' property cannot exceed 1 unless additional
CS lines are explicitly defined using GPIO descriptors.

Fixes: 2da187304e ("spi: add bindings for microchip mpfs spi")
Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Link: https://msgid.link/r/20240514104508.938448-2-prajna.rajendrakumar@microchip.com
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-05-27 01:33:14 +01:00
Rob Herring
d0dcd0ce84 dt-bindings: yamllint: Require a space after a comment '#'
Enable yamllint to check the preferred commenting style of requiring a
space after a comment character '#'. Fix the cases in the tree which
have a warning with this enabled. Most cases just need a space after the
'#'. A couple of cases with comments which were not intended to be
comments are revealed. Those were in ti,sa2ul.yaml, ti,cal.yaml, and
brcm,bcmgenet.yaml.

Acked-by: Jakub Kicinski <kuba@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # drm/msm
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20230303214223.49451-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
2023-03-08 09:04:53 -06:00
Naga Sureshkumar Relli
2ba464e5a3
spi: dt-binding: add coreqspi as a fallback for mpfs-qspi
Microchip's PolarFire SoC QSPI IP core is based on coreQSPI,
so add coreqspi as a fallback to mpfs-qspi.

Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220808064603.1174906-3-nagasuresh.relli@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15 12:17:37 +01:00
Naga Sureshkumar Relli
a5890c12ec
spi: dt-binding: document microchip coreQSPI
Add microchip coreQSPI compatible string and update the title/description
to reflect this addition.

Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220808064603.1174906-2-nagasuresh.relli@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15 12:17:36 +01:00
Rob Herring
6aa27071e4
spi: dt-bindings: Fix unevaluatedProperties warnings in examples
The 'unevaluatedProperties' schema checks is not fully working and doesn't
catch some cases where there's a $ref to another schema. A fix is pending,
but results in new warnings in examples.

'spi-max-frequency' is supposed to be a per SPI peripheral device property,
not a SPI controller property, so drop it.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220526014141.2872567-1-robh@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-06 12:32:28 +01:00
Conor Dooley
2da187304e
spi: add bindings for microchip mpfs spi
Add device tree bindings for the {q,}spi controller on
the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220117110755.3433142-7-conor.dooley@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-01-24 13:32:08 +00:00