McBSP's data delay can be configured from 0 to 2 bit clock periods. 0 is
used for DSP_B format, 1 for DSP_A format. A data delay of 2 bit clock
periods can be used to interface to 'T1 framing' devices where data
stream is preceded by a 'framing bit'. This 2 bit clock data delay is
not described in the bindings.
Add two flags 'ti,T1-framing-[rx/tx]' to enable a data delay of 2
bit clock periods in reception or transmission.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
Link: https://msgid.link/r/20240402071213.11671-13-bastien.curutchet@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The McBSP uses an internal sample rate generator to provide bit clock
or frame clock. This sample rate generator can be programmed to be
driven by McBSP's internal clock source or by an external clock source
(located on CLKS pin). The external clock source is not described in
the bindings.
Add an optional clock item that allows to select an external clock as
sample rate generator's input.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
Link: https://msgid.link/r/20240402071213.11671-3-bastien.curutchet@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Convert the binding for McBSP controllers for TI SoCs from txt
to YAML schema.
Add properties 'clocks', 'clock-names', 'power-domains' and
'#sound-dai-cells' which were missing from the txt file.
Add '#sound-dai-cells' and 'clocks' in the example which were missing
from the txt file.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
Link: https://msgid.link/r/20240402071213.11671-2-bastien.curutchet@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
