The Versal NET (Networked Adaptive Compute Acceleration Platform) from
AMD/Xilinx is a next-generation adaptive platform designed for high
performance computing, networking, and AI acceleration. It is part of the
Versal ACAP (Adaptive Compute Acceleration Platform) family.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6e4486141cf9b1d36b03624cc73621b2e3bba894.1738657826.git.michal.simek@amd.com
When DT overlay is applied at run time compatible string or model AFAIK is
not updated. But when fdtoverlay tool is used it actually creates full
description for used SOM and carrier card(CC). That's why there is no
reason to use generic SOM name and its compatible strings because they are
not properly reflected in newly created DT.
Composing dt overlays together was introduced by commit 7a4c31ee87
("arm64: zynqmp: Add support for Xilinx Kria SOM board") and later renamed
by commit 45fe0dc4ea ("arm64: xilinx: Use zynqmp prefix for SOM dt
overlays").
DTB selection is done prior booting OS that's why there is no need to do
run time composition for SOM and CC combination. And user space can use
compatible string and all listed revisions to figured it out which SOM and
CC combinations OS is running at.
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/14c184225cc4f0a61da5f8c98bc0767f8deba0df.1706019781.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Revision 2 is SW compatible with revision 1 but it is necessary to reflect
it in model and compatible properties which are parsed by user space.
Rev 2 has improved a power on boot reset and MIO34 shutdown glich
improvement done via an additional filter in the GreenPak chip.
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/90e1a393154c3d87e8ee7dc9eef07fc937c1eaf7.1706019397.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor. Processor can
be used with standard AMD/Xilinx IPs including interrupt controller and
timer.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
All Xilinx boards can hosts also soft core CPUs like MicroBlaze or
MicroBlaze V (RISC-V ISA) that's why move boards description from arm
folder to soc folder.
Similar change was done for Renesas by commit c27ce08b80 ("dt-bindings:
soc: renesas: Move renesas.yaml from arm to soc").
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
