Commit Graph

2 Commits

Author SHA1 Message Date
Théo Lebrun
a370b2d22d dt-bindings: soc: mobileye: set #clock-cells = <1> for all compatibles
Some compatibles expose a single clock. For those, we used to let them
using `#clock-cells = <0>` (ie <&olb> reference rather than <&olb 0>).

Switch away from that: enforce a cell for all compatibles. This is more
straight forward, and avoids devicetree changes whenever a compatible
goes from exposing a single clock to multiple ones. Also, dt-bindings
get simpler.

*This is an ABI break*. Change it while EyeQ5 platform support is at its
infancy, without any user. More clocks might hide in each OLB as some
registers are still unknown.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-1-84cfefb3f485@bootlin.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-14 14:52:26 -08:00
Théo Lebrun
bde4b22dc5 dt-bindings: soc: mobileye: add EyeQ OLB system controller
Add documentation to describe the "Other Logic Block" system-controller.
It deals with three platforms: EyeQ5, EyeQ6L and EyeQ6H. First two have
a single instance, whereas EyeQ6H has seven named instances.

Features provided are:
 - Clocks, children to main crystal. Some PLLs and divider clocks.
 - Resets. Some instances DO NOT have reset.
 - Pinctrl. Only EyeQ5 has such feature.

Those are NOT the only features exposed in OLB system-controllers! Many
individual registers, related to IP block integration, can be found.
Additional features will be exposed over time.

We simplify devicetree phandles to OLB in two ways:

 - Compatibles exposing a single clock do not ask for a index argument.
   This means we use EyeQ6H OLB south (it has four clocks):

      clocks = <&olb_south EQ6HC_SOUTH_PLL_PER>;

   But use EyeQ6H OLB east (it has one clock):

      clocks = <&olb_east>;

 - Compatibles exposing a single reset domain do not ask for a domain
   index, only a reset index.
   This means we use EyeQ5 OLB (it has three domains):

     resets = <&olb 0 10>;

   But use EyeQ6H west reset (it has one domain):

      resets = <&olb_west 3>;

About pinctrl subnodes: all pins have two functionality, either GPIO or
something-else. The latter is pin dependent, we express constraints
using many if-then.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2024-07-03 17:15:47 +02:00