The Aspeed pinctrl bindings are missing an additionalProperties/
unevaluatedProperties schemas on the child pin mux nodes which means any
undefined properties are allowed. In addition, using
'additionalProperties' for child nodes with any name works better than a
pattern matching everything with an if/then schema to select nodes only.
With 'additionalProperties' added, 'pins' and 'bias-disable'
properties need to be added as they were not defined. A $ref to
pinmux-node.yaml which defines the common property types was also
missing.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230819010907.916061-1-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
'phandle' properties are implicitly supported on all nodes, so it
shouldn't be listed in schemas.
dtschema had a bug where 'phandle' and other implicit properties weren't
being added under 'additionalProperties' schemas. That was fixed in
v2023.07 release.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230819010946.916772-1-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix typos in Documentation/devicetree/bindings. The changes are in
descriptions or comments where they shouldn't affect functionality.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20230814212822.193684-3-helgaas@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
1. Add support for the SM6115 and SM8350 LPASS (Low Power Audio
SubSystem) TLMM pin controllers.
2. Add bindings for the Qualcomm PMC8180 and PMC8180C PMICs GPIO pin
controllers.
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Merge tag 'qcom-pinctrl-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel
Qualcomm pinctrl changes for v6.6
1. Add support for the SM6115 and SM8350 LPASS (Low Power Audio
SubSystem) TLMM pin controllers.
2. Add bindings for the Qualcomm PMC8180 and PMC8180C PMICs GPIO pin
controllers.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Due to lack of maintenance and stall of development for a few years now,
and since no new features will ever be added upstream, remove the
OX810 and OX820 pinctrl bindings.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230814-topic-oxnas-upstream-remove-v3-2-04a0c5cdda52@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the "ti,am654-padconf" compatible to support the new wakeup enable and
status bits positions on K3 family SOCs that support the IO daisychain
feature.
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230808102207.130177-2-d-gole@ti.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Update binding for yaml and remove the old related txt bindings. Note that
we are also adding the undocumented pinctrl-single,slew-rate property. And
we only use the first example from the old binding.
As we are mostly using a generic compatible across various SoCs, let's not
start adding matches for random pin group node naming. Let's standardize on
pin group node name ending in -pins with an optional instance number
suffix.
As a pin group may have additional pins added to it later on, let's always
use -pins rather than -pin for the gropu name.
Most of the dts files have been updated already for the pin group node
names with a few changes still pending.
Cc: Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230721082654.27036-1-tony@atomide.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add 'output-enable' configuration parameter to the properties list.
Using these pinctrl properties observed hang issues with older Xilinx
ZynqMP Platform Management Firmware, hence reverted the patch previously.
Commit ff8356060e ("Revert "dt-bindings: pinctrl-zynqmp: Add
output-enable configuration"").
Support for configuring these properties added in Xilinx ZynqMP Platform
Management firmware(PMUFW) Configuration Set version 2.0. Linux firmware
driver checks if the configuration is supported by the PMUFW when it gets
request for TRISTATE configuration from pinctrl driver. If it supports,
then calls will be made otherwise it returns error.
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230731095026.3766675-4-sai.krishna.potthuri@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Document qcom,pmc8180-gpio and qcom,pmc8180c-gpio compatibles already
used in DTS and in the same binding in allOf:if:then section for
narrowing available GPIOs:
sc8180x-primus.dtb: pmic@4: gpio@c000:compatible:0: 'qcom,pmc8180c-gpio' is not one of ...
Fixes: 04bed6407e ("dt-bindings: pinctrl: qcom,pmic-gpio: describe gpio-line-names")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230720083539.73675-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Add bindings for pin controller in SM6115 Low Power Audio SubSystem
LPASS).
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-1-d4883831a858@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Alternative function 'gpio' is not listed in the constants for pin
configuration, so adding this constant to the list.
Cc: stable@vger.kernel.org
Fixes: 9a2aaee23c ("dt-bindings: pinctrl: describe sa8775p-tlmm")
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230719110344.19983-1-quic_shazhuss@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a new compatible name for Amlogic C3 pin controller, and add
a new dt-binding header file which document the detail pin names.
Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230714122441.3098337-2-huqiang.qin@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds support for an optional reset pin.
The reset pin is used to bring the chip into a known state and has an
internal pull-down, allowing it to be left floating if not needed.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230714081902.2621771-1-Naresh.Solanki@9elements.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for the pmx75 GPIO support to the Qualcomm PMIC GPIO
binding.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/1688707209-30151-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for the pm7550ba GPIO support to the Qualcomm PMIC GPIO
binding.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/1688707209-30151-2-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
No core changes this time.
New drivers:
- Tegra234 support.
- Qualcomm IPQ5018 support.
- Intel Meteor Lake-S support.
- Qualcomm SDX75 subdriver.
- Qualcomm SPMI-based PM8953 support.
Improvements:
- Fix up support for GPIO3 on the AXP209.
- Push-pull drive configuration support for the AT91 PIO4.
- Fix misc non-urgent bugs in the AMD driver.
- Misc non-urgent improved error handling.
- Misc janitorial and minor improvements.
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Merge tag 'pinctrl-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"No core changes this time
New drivers:
- Tegra234 support
- Qualcomm IPQ5018 support
- Intel Meteor Lake-S support
- Qualcomm SDX75 subdriver
- Qualcomm SPMI-based PM8953 support
Improvements:
- Fix up support for GPIO3 on the AXP209
- Push-pull drive configuration support for the AT91 PIO4
- Fix misc non-urgent bugs in the AMD driver
- Misc non-urgent improved error handling
- Misc janitorial and minor improvements"
* tag 'pinctrl-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits)
pinctrl: cherryview: Drop goto label
pinctrl: baytrail: invert if condition
pinctrl: baytrail: add warning for BYT_VAL_REG retrieval failure
pinctrl: baytrail: reduce scope of spinlock in ->dbg_show() hook
pinctrl: tegra: avoid duplicate field initializers
dt-bindings: pinctrl: qcom,sdx65-tlmm: add pcie_clkreq function
pinctrl: mlxbf3: remove broken Kconfig 'select'
pinctrl: spear: Remove unused of_gpio.h inclusion
pinctrl: lantiq: Remove unused of_gpio.h inclusion
pinctrl: at91-pio4: check return value of devm_kasprintf()
pinctrl: microchip-sgpio: check return value of devm_kasprintf()
pinctrl: freescale: Fix a memory out of bounds when num_configs is 1
pinctrl: intel: refine ->irq_set_type() hook
pinctrl: intel: refine ->set_mux() hook
pinctrl: baytrail: Use str_hi_lo() helper
lib/string_choices: Add str_high_low() helper
lib/string_helpers: Split out string_choices.h
lib/string_helpers: Add missing header files to MAINTAINERS database
pinctrl: npcm7xx: Add missing check for ioremap
pinctrl:sunplus: Add check for kmalloc
...
There are two new SoC families this time, and both appear fairly similar:
The Nuvoton MA35D1 and the STMicroelectronics STM32MP2 are both dual-core
Cortex-A35 based chips for the low-power industrial embedded market,
and they mark the first 64-bit product in a widely used family of 32-bit
Arm MCUs and SoCs.
The way into the kernel is completely different here: The team at ST has
a long history of working upstream with their STM32MP1 and other SoCs,
and they produced a complete port to arm64 together with the initial
announcement. Nuvoton also has multiple SoC product lines with current
or previous upstream support, but those are maintained by third parties
and are unrelated. The patch series from Nuvoton's Jacky Huang had to
go through many revisisions to get to this point and is still missing
a few drivers including the serial port for the moment.
The branch contains the devicetree files as well as all the code changes,
in order to have something that can be tested standalone.
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Merge tag 'soc-newsoc-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new ARM SoC support from Arnd Bergmann:
"There are two new SoC families this time, and both appear fairly
similar: The Nuvoton MA35D1 and the STMicroelectronics STM32MP2 are
both dual-core Cortex-A35 based chips for the low-power industrial
embedded market, and they mark the first 64-bit product in a widely
used family of 32-bit Arm MCUs and SoCs.
The way into the kernel is completely different here: The team at ST
has a long history of working upstream with their STM32MP1 and other
SoCs, and they produced a complete port to arm64 together with the
initial announcement. Nuvoton also has multiple SoC product lines with
current or previous upstream support, but those are maintained by
third parties and are unrelated. The patch series from Nuvoton's Jacky
Huang had to go through many revisisions to get to this point and is
still missing a few drivers including the serial port for the moment.
The branch contains the devicetree files as well as all the code
changes, in order to have something that can be tested standalone"
* tag 'soc-newsoc-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
clk: nuvoton: Use clk_parent_data instead of string for parent clock
clk: nuvoton: Update all constant hex values to lowercase
clk: nuvoton: Add clk-ma35d1.h for driver extern functions
remoteproc: stm32: use correct format strings on 64-bit
MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE
arm64: defconfig: enable ARCH_STM32 and STM32 serial driver
arm64: dts: st: add stm32mp257f-ev1 board support
dt-bindings: stm32: document stm32mp257f-ev1 board
arm64: dts: st: introduce stm32mp25 pinctrl files
arm64: dts: st: introduce stm32mp25 SoCs family
arm64: introduce STM32 family on Armv8 architecture
dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon
pinctrl: stm32: add stm32mp257 pinctrl support
dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages
Documentation/process: add soc maintainer handbook
reset: RESET_NUVOTON_MA35D1 should depend on ARCH_MA35
reset: Add Nuvoton ma35d1 reset driver support
clk: nuvoton: Add clock driver for ma35d1 clock controller
arm64: dts: nuvoton: Add initial ma35d1 device tree
dt-bindings: serial: Document ma35d1 uart controller
...
The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for each
SoC vendor, following the same scheme that is used on arm64, mips and
riscv. This has been discussed for many years, but so far we never did
this as there was a plan to move the files out of the kernel entirely,
which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along
with their device drivers.
* The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the time.
* Amlogic C3 is a Cortex-A35 based smart IP camera chip
* Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
* Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
* Qualcomm SDX75 is the latest generation modem chip that is used
as a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
* Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the Xuantie
C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those included
there are 39 new board files, but only five more 32-bit this time, probably
a new low:
* Marantec Maveo board based on dhcor imx6ull module
* Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
* Epson Moverio BT-200 AR glasses based on TI OMAP4
* PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
* ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than
we had in the recent releases:
* Three boards based on NXP i.MX8: Emtop SoM & Baseboard,
NXP i.MX8MM EVKB board and i.MX8MP based Gateworks Venice
gw7905-2x device.
* NVIDIA IGX Orin and Jetson Orin Nano boards, both based on
tegra234
* Qualcomm gains support for 6 reference boards on various members
of their IPQ networking SoC series, as well as the Sony Xperia M4
Aqua phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board
on top of the various reference platforms for their new chips.
* Rockchips support for several newer boards: Indiedroid Nova (rk3588),
Edgeble Neural Compute Module 6B (rk3588), FriendlyARM NanoPi R2C
Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn Fastrhino R66S/R68S
(rk3568)
* TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex Verdin
family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
* continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
* support for devicetree overlays on at91, bcm283x
* significant additions to existing SoC support on mediatek, qualcomm,
ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST STM32MP1
As usual, a lot more detail is available in the individual merge
commits.
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Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC devicetree updates from Arnd Bergmann:
"The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for
each SoC vendor, following the same scheme that is used on arm64, mips
and riscv. This has been discussed for many years, but so far we never
did this as there was a plan to move the files out of the kernel
entirely, which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along with
their device drivers.
- The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the
time.
- Amlogic C3 is a Cortex-A35 based smart IP camera chip
- Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
- Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
- Qualcomm SDX75 is the latest generation modem chip that is used as
a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
- Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the
Xuantie C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those
included there are 39 new board files, but only five more 32-bit this
time, probably a new low:
- Marantec Maveo board based on dhcor imx6ull module
- Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
- Epson Moverio BT-200 AR glasses based on TI OMAP4
- PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
- ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than we had
in the recent releases:
- Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM
EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device.
- NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234
- Qualcomm gains support for 6 reference boards on various members of
their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua
phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top
of the various reference platforms for their new chips.
- Rockchips support for several newer boards: Indiedroid Nova
(rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM
NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn
Fastrhino R66S/R68S (rk3568)
- TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex
Verdin family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
- continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
- support for devicetree overlays on at91, bcm283x
- significant additions to existing SoC support on mediatek,
qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST
STM32MP1
As usual, a lot more detail is available in the individual merge
commits"
* tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits)
ARM: mvebu: fix unit address on armada-390-db flash
ARM: dts: Move .dts files to vendor sub-directories
kbuild: Support flat DTBs install
ARM: dts: Add .dts files missing from the build
ARM: dts: allwinner: Use quoted #include
ARM: dts: lan966x: kontron-d10: add PHY interrupts
ARM: dts: lan966x: kontron-d10: fix SPI CS
ARM: dts: lan966x: kontron-d10: fix board reset
ARM: dts: at91: Enable device-tree overlay support for AT91 boards
arm: dts: Enable device-tree overlay support for AT91 boards
arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller
ARM: dts: at91: use generic name for shutdown controller
ARM: dts: BCM5301X: Add cells sizes to PCIe nodes
dt-bindings: firmware: brcm,kona-smc: convert to YAML
riscv: dts: sort makefile entries by directory
riscv: defconfig: enable T-HEAD SoC
MAINTAINERS: add entry for T-HEAD RISC-V SoC
riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
riscv: dts: add initial T-HEAD TH1520 SoC device tree
riscv: Add the T-HEAD SoC family Kconfig option
...
DTS and driver already support pcie_clkreq function for a pin. Add it
to fix dtbs_check warning:
qcom-sdx65-mtp.dtb: pinctrl@f100000: pcie-ep-clkreq-default-state: 'oneOf' conditional failed, one must be fixed:
'bias-disable', 'drive-strength', 'function', 'pins' do not match any of the regexes: '-pins$', 'pinctrl-[0-9]+'
'pcie_clkreq' is not one of ['blsp_uart1', 'blsp_spi1', ... 'gpio']
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230617111809.129232-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The "qcom,paired" schema is all wrong. First, it's a list rather than an
object(dictionary). Second, it is missing a required type. The meta-schema
normally catches this, but schemas under "$defs" was not getting checked.
A fix for that is pending.
Fixes: f9a06b8109 ("dt-bindings: pinctrl: qcom,pmic-mpp: Convert qcom pmic mpp bindings to YAML")
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230418150606.1528107-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Simplify remaining bindings with usage of unevaluatedProperties. This
will have the same functional effect with less code.
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Merge tag 'qcom-pinctrl-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel
Qualcomm pinctrl Devicetree bindings changes for v6.5
Simplify remaining bindings with usage of unevaluatedProperties. This
will have the same functional effect with less code.
Tegra234 contains two pin controllers. Document their compatible strings
and describe the list of pins and functions that they provide.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230605154230.2910847-2-thierry.reding@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for st,stm32mp257-pinctrl and st,stm32mp257-z-pinctrl.
Add packages AI, AK and AL (values : 0x100, 0x400 and 0x800)
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
@xilinx.com is still working but better to switch to new amd.com after
AMD/Xilinx acquisition.
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Acked-by: Damien Le Moal <dlemoal@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f5b2bd1e78407e4128fc8f0b5874ba723e710a88.1684245058.git.michal.simek@amd.com
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Link: https://lore.kernel.org/r/20230407184546.161168-35-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Link: https://lore.kernel.org/r/20230407184546.161168-18-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Link: https://lore.kernel.org/r/20230407184546.161168-25-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Link: https://lore.kernel.org/r/20230407184546.161168-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
- Add Conor Dooley as a DT binding maintainer
- Swap the order of parsing /memreserve/ and /reserved-memory nodes so
that the /reserved-memory nodes which have more information are
handled first
- Fix some property dependencies in riscv,pmu binding
- Update maintainers entries on a couple of bindings
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Merge tag 'devicetree-fixes-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree fixes from Rob Herring:
- Add Conor Dooley as a DT binding maintainer
- Swap the order of parsing /memreserve/ and /reserved-memory nodes so
that the /reserved-memory nodes which have more information are
handled first
- Fix some property dependencies in riscv,pmu binding
- Update maintainers entries on a couple of bindings
* tag 'devicetree-fixes-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
MAINTAINERS: add Conor as a dt-bindings maintainer
dt-bindings: perf: riscv,pmu: fix property dependencies
dt-bindings: xilinx: Remove Naga from memory and mtd bindings
of: fdt: Scan /memreserve/ last
dt-bindings: clock: r9a06g032-sysctrl: Change maintainer to Fabrizio Castro
dt-bindings: pinctrl: renesas,rzv2m: Change maintainer to Fabrizio Castro
dt-bindings: pinctrl: renesas,rzn1: Change maintainer to Fabrizio Castro
dt-bindings: i2c: renesas,rzv2m: Change maintainer to Fabrizio Castro
Core changes:
- Make a lot of pin controllers with GPIO and irqchips immutable,
i.e. not living structs, but const structs. This is driving a
changed initiated by the irqchip maintainers.
New drivers:
- New driver for the NXP S32 SoC pin controller
- As part of a thorough cleanup and restructuring of the
Ralink/Mediatek drivers, the Ralink MIPS pin control drivers
were folded into the Mediatek directory and the family is
renamed "mtmips". The Ralink chips live on as Mediatek MIPS
family where new variants can be added. As part of this work
also the device tree bindings were reworked.
- New subdriver for the Qualcomm SM7150 SoC.
- New subdriver for the Qualcomm IPQ9574 SoC.
- New driver for the nVidia BlueField-3 SoC.
- Support for the Qualcomm PMM8654AU mixed signal circuit GPIO.
- Support for the Qualcomm PMI632 mixed signal circuit GPIO.
Improvements:
- Add some missing pins and generic cleanups on the Renesas
r8a779g0 and r8a779g0 pin controllers. Generic Renesas
extension for power source selection on several SoCs.
- Misc cleanups for the Atmel AT91 and AT91-PIO4 pin
controllers
- Make the GPIO mode work on the Qualcomm SM8550-lpass-lpi
driver.
- Several device tree binding cleanups as the binding
YAML syntax is solidifying.
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Merge tag 'pinctrl-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Mostly drivers! Nothing special: some new Qualcomm chips as usual, and
the new NXP S32 and nVidia BlueField-3.
Core changes:
- Make a lot of pin controllers with GPIO and irqchips immutable,
i.e. not living structs, but const structs. This is driving a
changed initiated by the irqchip maintainers.
New drivers:
- New driver for the NXP S32 SoC pin controller
- As part of a thorough cleanup and restructuring of the
Ralink/Mediatek drivers, the Ralink MIPS pin control drivers were
folded into the Mediatek directory and the family is renamed
"mtmips". The Ralink chips live on as Mediatek MIPS family where
new variants can be added. As part of this work also the device
tree bindings were reworked.
- New subdriver for the Qualcomm SM7150 SoC.
- New subdriver for the Qualcomm IPQ9574 SoC.
- New driver for the nVidia BlueField-3 SoC.
- Support for the Qualcomm PMM8654AU mixed signal circuit GPIO.
- Support for the Qualcomm PMI632 mixed signal circuit GPIO.
Improvements:
- Add some missing pins and generic cleanups on the Renesas r8a779g0
and r8a779g0 pin controllers. Generic Renesas extension for power
source selection on several SoCs.
- Misc cleanups for the Atmel AT91 and AT91-PIO4 pin controllers
- Make the GPIO mode work on the Qualcomm SM8550-lpass-lpi driver.
- Several device tree binding cleanups as the binding YAML syntax is
solidifying"
* tag 'pinctrl-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (153 commits)
pinctrl-bcm2835.c: fix race condition when setting gpio dir
dt-bindings: pinctrl: qcom,sm8150: Drop duplicate function value "atest_usb2"
dt-bindings: pinctrl: qcom: Add few missing functions
pinctrl: qcom: spmi-gpio: Add PMI632 support
dt-bindings: pinctrl: qcom,pmic-gpio: add PMI632
pinctrl: wpcm450: select MFD_SYSCON
pinctrl: qcom ssbi-gpio: Convert to immutable irq_chip
pinctrl: qcom ssbi-mpp: Convert to immutable irq_chip
pinctrl: qcom spmi-mpp: Convert to immutable irq_chip
pinctrl: plgpio: Convert to immutable irq_chip
pinctrl: pistachio: Convert to immutable irq_chip
pinctrl: pic32: Convert to immutable irq_chip
pinctrl: sx150x: Convert to immutable irq_chip
pinctrl: stmfx: Convert to immutable irq_chip
pinctrl: st: Convert to immutable irq_chip
pinctrl: mcp23s08: Convert to immutable irq_chip
pinctrl: equilibrium: Convert to immutable irq_chip
pinctrl: npcm7xx: Convert to immutable irq_chip
pinctrl: armada-37xx: Convert to immutable irq_chip
pinctrl: nsp: Convert to immutable irq_chip
...
The devicetree changes overall are again dominated by the Qualcomm
Snapdragon platform that weighs in at over 300 changesets, but there
are many updates across other platforms as well, notably Mediatek, NXP,
Rockchips, Renesas, TI, Samsung and ST Microelectronics. These all
add new features for existing machines, as well as new machines and
SoCs.
The newly added SoCs are:
- Allwinner T113-s, an Cortex-A7 based variant of the RISC-V
based D1 chip.
- StarFive JH7110, a RISC-V SoC based on the Sifive U74 core
like its JH7100 predecessor, but with additional CPU cores
and a GPU.
- Apple M2 as used in current Macbook Air/Pro and Mac Mini
gets added, with comparable support as its M1 predecessor.
- Unisoc UMS512 (Tiger T610) is a midrange smartphone SoC
- Qualcomm IPQ5332 and IPQ9574 are Wi-Fi 7 networking SoCs,
based on the Cortex-A53 and Cortex-A73 cores, respectively.
- Qualcomm sa8775p is an automotive SoC derived from the
Snapdragon family.
Including the initial board support for the added SoC platforms,
there are 52 new machines. The largest group are 19 boards
industrial embedded boards based on the NXP i.MX6 (32-bit)
and i.MX8 (64-bit) families.
Others include:
- Two boards based on the Allwinner f1c200s ultra-low-cost chip
- Three "Banana Pi" variants based on the Amlogic g12b
(A311D, S922X) SoC.
- The Gl.Inet mv1000 router based on Marvell Armada 3720
- A Wifi/LTE Dongle based on Qualcomm msm8916
- Two robotics boards based on Qualcomm QRB chips
- Three Snapdragon based phones made by Xiaomi
- Five developments boards based on various Rockchip SoCs,
including the rk3588s-khadas-edge2 and a few NanoPi
models
- The AM625 Beagleplay industrial SBC
Another 14 machines get removed: both boards for the obsolete "oxnas"
platform, three boards for the Renesas r8a77950 SoC that were only for
pre-production chips, and various chromebook models based on the Qualcomm
Sc7180 "trogdor" design that were never part of products.
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Merge tag 'soc-dt-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC devicetree updates from Arnd Bergmann:
"The devicetree changes overall are again dominated by the Qualcomm
Snapdragon platform that weighs in at over 300 changesets, but there
are many updates across other platforms as well, notably Mediatek,
NXP, Rockchips, Renesas, TI, Samsung and ST Microelectronics. These
all add new features for existing machines, as well as new machines
and SoCs.
The newly added SoCs are:
- Allwinner T113-s, an Cortex-A7 based variant of the RISC-V based D1
chip.
- StarFive JH7110, a RISC-V SoC based on the Sifive U74 core like its
JH7100 predecessor, but with additional CPU cores and a GPU.
- Apple M2 as used in current Macbook Air/Pro and Mac Mini gets
added, with comparable support as its M1 predecessor.
- Unisoc UMS512 (Tiger T610) is a midrange smartphone SoC
- Qualcomm IPQ5332 and IPQ9574 are Wi-Fi 7 networking SoCs, based on
the Cortex-A53 and Cortex-A73 cores, respectively.
- Qualcomm sa8775p is an automotive SoC derived from the Snapdragon
family.
Including the initial board support for the added SoC platforms, there
are 52 new machines. The largest group are 19 boards industrial
embedded boards based on the NXP i.MX6 (32-bit) and i.MX8 (64-bit)
families.
Others include:
- Two boards based on the Allwinner f1c200s ultra-low-cost chip
- Three 'Banana Pi' variants based on the Amlogic g12b (A311D, S922X)
SoC.
- The Gl.Inet mv1000 router based on Marvell Armada 3720
- A Wifi/LTE Dongle based on Qualcomm msm8916
- Two robotics boards based on Qualcomm QRB chips
- Three Snapdragon based phones made by Xiaomi
- Five developments boards based on various Rockchip SoCs, including
the rk3588s-khadas-edge2 and a few NanoPi models
- The AM625 Beagleplay industrial SBC
Another 14 machines get removed: both boards for the obsolete 'oxnas'
platform, three boards for the Renesas r8a77950 SoC that were only for
pre-production chips, and various chromebook models based on the
Qualcomm Sc7180 'trogdor' design that were never part of products"
* tag 'soc-dt-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (836 commits)
arm64: dts: rockchip: Add support for volume keys to rk3399-pinephone-pro
arm64: dts: rockchip: Add vdd_cpu_big regulators to rk3588-rock-5b
arm64: dts: rockchip: Use generic name for es8316 on Pinebook Pro and Rock 5B
arm64: dts: rockchip: Drop RTC clock-frequency on rk3588-rock-5b
arm64: dts: apple: t8112: Add PWM controller
arm64: dts: apple: t600x: Add PWM controller
arm64: dts: apple: t8103: Add PWM controller
arm64: dts: rockchip: Add pinctrl gpio-ranges for rk356x
ARM: dts: nomadik: Replace deprecated spi-gpio properties
ARM: dts: aspeed-g6: Add UDMA node
ARM: dts: aspeed: greatlakes: add mctp device
ARM: dts: aspeed: greatlakes: Add gpio names
ARM: dts: aspeed: p10bmc: Change power supply info
arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMM050 Magnetometer
arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMA255 Accelerometer
arm64: dts: mediatek: mt6795: Add tertiary PWM node
arm64: dts: rockchip: add panel to Anbernic RG353 series
dt-bindings: arm: Add Data Modul i.MX8M Plus eDM SBC
dt-bindings: arm: fsl: Add chargebyte Tarragon
dt-bindings: vendor-prefixes: add chargebyte
...
The enum value "atest_usb2" appears twice. Remove the duplicate. The
meta-schema normally catches these, but schemas under "$defs" was not
getting checked. A fix for that is pending.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230418150613.1528233-1-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Devicetree for the QCM2210/QCM2290 is introduced. Support for the RB1
board is introduced on QRB2210, RB2 on QRB4210, the AL02 board on
IPQ9574, the MI01.6 board is introduced on IPQ5332 and initial support
for Xiaomi Mi A3 is introduced on SM6125.
Support for the output-enable/disable flag is introduced in the
pinctrl-msm driver, and the non-standard "input-enable" is dropped from
a range of platforms.
A wide range of smaller fixes are introduced, based on Devicetree
validation.
MSM8953 gains LPASS, MPSS and Wireless subsystem support.
The iommus property is removed from PCIe nodes in all platforms, as the
only the child devices should be associated with iommu groups, through
the existing iommu-map property.
A few QUP instances are introduced on the IPQ5332 platform, and support
for the MI01.6 board is introduced.
The reserved-memory map on Huawei Nexus 6P is updated with the addition
of splash screen framebuffer memory and adjustment to the reserved
memory region overlapping the smem region.
Regulators are introduces for the SA8775P Ride platform.
A regulator is marked always-on, for correctness, on Trogdor. Pinconf
fixes are introduced to both sc7180 and sc7280 devices. A dedicated
reviewers list is added for boards relevant to the Chromebook engineers.
A set of pinconf fixes are introduced for sc8280xp, labels are
introduced for Soundwire nodes.
The sensor core remoteproc and FastRPC thereon, is introduce in SDM845
and enabled for OnePlus 6/6T and Shift Shift6mq.
RMTFS, remoteprocs, ath10k and ramoops is introduced for the Lenovo Tab
P11.
UFS support is introduced on SM6125.
SM8150 no longer defines the GPU to be in headless mode by default, GPU
speedbins are introduced.
GPU speedbins are introduced for SM8250 as well, as is support for
display on Xiaomi Mi Pad 5 Pro, with two different panels supported.
Soundwire controllers, ADSP audio codec macros and the Inline Crypto
Engine support is added to the SM8550 platform.
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Merge tag 'qcom-arm64-for-6.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
More Qualcomm ARM64 Devicetree updated for v6.4
Devicetree for the QCM2210/QCM2290 is introduced. Support for the RB1
board is introduced on QRB2210, RB2 on QRB4210, the AL02 board on
IPQ9574, the MI01.6 board is introduced on IPQ5332 and initial support
for Xiaomi Mi A3 is introduced on SM6125.
Support for the output-enable/disable flag is introduced in the
pinctrl-msm driver, and the non-standard "input-enable" is dropped from
a range of platforms.
A wide range of smaller fixes are introduced, based on Devicetree
validation.
MSM8953 gains LPASS, MPSS and Wireless subsystem support.
The iommus property is removed from PCIe nodes in all platforms, as the
only the child devices should be associated with iommu groups, through
the existing iommu-map property.
A few QUP instances are introduced on the IPQ5332 platform, and support
for the MI01.6 board is introduced.
The reserved-memory map on Huawei Nexus 6P is updated with the addition
of splash screen framebuffer memory and adjustment to the reserved
memory region overlapping the smem region.
Regulators are introduces for the SA8775P Ride platform.
A regulator is marked always-on, for correctness, on Trogdor. Pinconf
fixes are introduced to both sc7180 and sc7280 devices. A dedicated
reviewers list is added for boards relevant to the Chromebook engineers.
A set of pinconf fixes are introduced for sc8280xp, labels are
introduced for Soundwire nodes.
The sensor core remoteproc and FastRPC thereon, is introduce in SDM845
and enabled for OnePlus 6/6T and Shift Shift6mq.
RMTFS, remoteprocs, ath10k and ramoops is introduced for the Lenovo Tab
P11.
UFS support is introduced on SM6125.
SM8150 no longer defines the GPU to be in headless mode by default, GPU
speedbins are introduced.
GPU speedbins are introduced for SM8250 as well, as is support for
display on Xiaomi Mi Pad 5 Pro, with two different panels supported.
Soundwire controllers, ADSP audio codec macros and the Inline Crypto
Engine support is added to the SM8550 platform.
* tag 'qcom-arm64-for-6.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (85 commits)
arm64: dts: qcom: Add base qrb4210-rb2 board dts
arm64: dts: qcom: sm8550: add Soundwire controllers
arm64: dts: qcom: sm8250: Add GPU speedbin support
arm64: dts: qcom: sm8150: Add GPU speedbin support
arm64: dts: qcom: sm8150: Don't start Adreno in headless mode
arm64: dts: qcom: ipq5332: add support for the RDP468 variant
arm64: dts: qcom: sdm630: move DSI opp-table out of DSI node
arm64: dts: qcom: sm6115p-j606f: Enable ATH10K WiFi
arm64: dts: qcom: sm6115p-j606f: Enable remoteprocs
arm64: dts: qcom: sm6115: Add RMTFS
arm64: dts: qcom: sm6115-j606f: Add ramoops node
arm64: dts: qcom: msm8916-thwc-ufi001c: add function to pin config
arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node
arm64: dts: MSM8953: Add lpass nodes
arm64: dts: MSM8953: Add mpss nodes
arm64: dts: MSM8953: Add wcnss nodes
arm64: dts: qcom: sm8350: remove superfluous "input-enable"
arm64: dts: qcom: sm8150: remove superfluous "input-enable"
arm64: dts: qcom: apq8016: remove superfluous "input-enable"
arm64: dts: qcom: sc8280xp-lenovo-thinkpad: correct pin drive-strength
...
Link: https://lore.kernel.org/r/20230414031550.2412379-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cleanup and improvement of the bindings to use "unevaluatedProperties"
instead of "additionalProperties", which allows to accept all the
properties already parsed by referenced common qcom,tlmm-common.yaml
schema.
That common qcom,tlmm-common.yaml binding is going to remove
"input-enable" property, thus using "unevaluatedProperties" allows such
change to propagate to other bindings automatically.
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Merge tag 'qcom-pinctrl-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel
Qualcomm pinctrl Devicetree bindings changes for v6.4
Cleanup and improvement of the bindings to use "unevaluatedProperties"
instead of "additionalProperties", which allows to accept all the
properties already parsed by referenced common qcom,tlmm-common.yaml
schema.
That common qcom,tlmm-common.yaml binding is going to remove
"input-enable" property, thus using "unevaluatedProperties" allows such
change to propagate to other bindings automatically.
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-40-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-39-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-38-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-37-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-36-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-34-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-33-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-32-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-31-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-30-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-29-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
This also fixes warnings like:
sdm845-cheza-r1.dtb: pinctrl@3400000: qspi-sleep-state: 'oneOf' conditional failed, one must be fixed:
'output-disable' does not match any of the regexes: 'pinctrl-[0-9]+'
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-28-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-27-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-26-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-24-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
This also fixes warnings like:
sc7280-herobrine-evoker.dtb: pinctrl@f100000: qspi-sleep-state: 'oneOf' conditional failed, one must be fixed:
'output-disable' does not match any of the regexes: 'pinctrl-[0-9]+'
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-23-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
This also fixes warnings like:
c7180-trogdor-coachz-r1.dtb: pinctrl@3500000: qspi-sleep-state: 'oneOf' conditional failed, one must be fixed:
'output-disable' does not match any of the regexes: 'pinctrl-[0-9]+'
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-22-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-21-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-20-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-19-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-17-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-16-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-15-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-14-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-13-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-12-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-11-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-10-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-9-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-8-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All Qualcomm SoC Top Level Mode Multiplexer pin controllers have similar
capabilities regarding pin properties, thus we can just accept entire
set provided by qcom,tlmm-common.yaml schema.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230407184546.161168-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This SoC is able to drive the following output current:
- 2 mA
- 4 mA
- 6 mA
- 8 mA
- 10 mA
- 12 mA
- 14 mA
- 16 mA
Then drive-strength property is set with enum to reflect its HW capability.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20230327-cleanup-pinctrl-binding-v3-3-6f56d5c7a8de@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In order to be more generic, "mediatek,pull-up-adv" and
"mediatek,pull-down-adv" should be deprecated. Use "bias-pull-up" and
"bias-pull-down" instead.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230327-cleanup-pinctrl-binding-v3-2-6f56d5c7a8de@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Deprecate mediatek,drive-strength-adv which shall not exist, that was an
unnecessary property that leaked upstream from downstream kernels and
there's no reason to use it.
The generic property drive-strength-microamp should be used instead.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230327-cleanup-pinctrl-binding-v3-1-6f56d5c7a8de@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a new compatible for the GPIO controller on the pm8654au PMIC. It
has 12 pins with no holes.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230327125316.210812-13-brgl@bgdev.pl
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Remove Thunder Bay specific code as the product got cancelled
and there are no end customers or users.
Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
Link: https://lore.kernel.org/r/20230403120235.939-2-lakshmi.sowjanya.d@intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This code are marked as deprecated since kernel 4.5[1]. Downstream OpenWRT
and upstream switched to the new string compatible 7 years ago. The old
compatible strings can safely be dropped.
[1] commit be14811c03 ("pinctrl/lantiq: introduce new dedicated devicetree bindings")
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230330212225.10214-2-olek2@wp.pl
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Cleanup bindings dropping unneeded quotes. Once all these are fixed,
checking for this can be enabled in yamllint.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Hector Martin <marcan@marcan.st>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de> #rockchip
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230330200402.2731992-1-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In the patch ("dt-bindings: pinctrl: qcom: tlmm should use
output-disable, not input-enable") we allowed setting "output-disable"
for TLMM pinctrl states. Let's also add "output-enable".
At first blush this seems a needless thing to do. Specifically:
- In Linux (and presumably any other OSes using the same device trees)
the GPIO/pinctrl driver knows to automatically enable the output
when a GPIO is changed to an output. Thus in most cases specifying
"output-enable" is superfluous and should be avoided.
- If we need to set a pin's default state we already have
"output-high" and "output-low" and these properties already imply
"output-enabled" (at least on the Linux Qualcomm TLMM driver).
However, there is one instance where "output-enable" seems like it
could be useful: sleep states. It's not uncommon to want to configure
pins as inputs (with appropriate pulls) when the driver controlling
them is in a low power state. Then we want the pins back to outputs
when the driver wants things running normally. To accomplish this we'd
want to be able to use "output-enable". Then the "default" state could
have "output-enable" and the "sleep" state could have
"output-disable".
NOTE: in all instances I'm aware of, we'd only want to use
"output-enable" on pins that are configured as "gpio". The Qualcomm
documentation that I have access to says that "output-enable" only
does something useful when in GPIO mode.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230323102605.7.I7874c00092115c45377c2a06f7f133356956686e@changeid
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As evidenced by the Qualcomm TLMM Linux driver, the TLMM IP block in
Qualcomm SoCs has a bit to enable/disable the output for a pin that's
configured as a GPIO but _not_ a bit to enable/disable an input
buffer. Current device trees that are specifying "input-enable" for
pins managed by TLMM are either doing so needlessly or are using it to
mean "output-disable".
Presumably the current convention of using "input-enable" to mean
"output-disable" stems from the fact that "output-disable" is a "new"
property from 2017. It was introduced in commit 425562429d
("pinctrl: generic: Add output-enable property"). The "input-enable"
handling in Qualcomm drivers is from 2015 introduced in commit
407f5e392f ("pinctrl: qcom: handle input-enable pinconf property").
Given that there's no other use for "input-enable" for TLMM, we can
still handle old device trees in code, but let's encourage people to
move to the proper / documented property by updating the bindings.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230323102605.6.I291ce0ba2c6ea80b341659c4f75a567a76dd7ca6@changeid
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This new SoC uses the same pinctrl hardware, so just add a new per-SoC
compatible.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
The controller supports 'bias-bus-hold' so add it to the binding.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230316105800.18751-1-johan+linaro@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Allow the common input-enable. This was missed with the
initial submission.
Fixes: 5147022214 ("dt-bindings: pinctrl: qcom: Add QCM2290 pinctrl bindings")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230314222705.2940258-1-konrad.dybcio@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The MT7628 and MT7688 SoCs contain different pin muxing information,
therefore, should be split. This can be done now that there are compatible
strings to distinguish them from other SoCs.
Split the schema out to mediatek,mt76x8-pinctrl.yaml.
Remove mediatek,mt76x8-pinctrl from mt7620.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-21-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The RT3352 and RT5350 SoCs each contain different pin muxing information,
therefore, should be split. This can be done now that there are compatible
strings to distinguish them from other SoCs.
Split the schema out to ralink,rt3352-pinctrl.yaml and
ralink,rt5350-pinctrl.yaml.
Remove ralink,rt3352-pinctrl and ralink,rt5350-pinctrl from rt305x.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-20-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Set second level patternProperties to '^.*mux.*$' and '^.*conf.*$' on
mediatek,mt7986-pinctrl.yaml to be on par with other schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-19-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix the location of the pinmux header files mentioned on the schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-17-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Change the style of description properties to plain style where there's no
need to preserve the line endings, and vice versa.
Fix capitalisation and indentation.
Fit the schemas to 80 columns for each line.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-16-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some schemas include "MediaTek", some "Mediatek". Rename all to "MediaTek"
to address the naming inconsistency.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-15-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rename pinctrl-mt8195.yaml to mediatek,mt8195-pinctrl.yaml to be on par
with the compatible string and other mediatek dt-binding schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-14-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rename pinctrl-mt8192.yaml to mediatek,mt8192-pinctrl.yaml to be on par
with the compatible string and other mediatek dt-binding schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-13-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rename pinctrl-mt8186.yaml to mediatek,mt8186-pinctrl.yaml to be on par
with the compatible string and other mediatek dt-binding schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-12-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rename mediatek,pinctrl-mt6795.yaml to mediatek,mt6795-pinctrl.yaml to be
on par with the compatible string and other mediatek dt-binding schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-11-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rename schemas of pin controllers for MediaTek MT7620 and MT7621 SoCs to be
on par with other pin controllers for MediaTek SoCs.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-10-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the new compatible strings for mt7620, mt76x8, and rt305x to be able to
properly document the pin muxing information of each SoC, or SoCs that use
the same pinmux data.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-9-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Move additionalProperties to the top. It's easier to read than after a long
indented section.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-7-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The description of second IO address is a bit confusing. It is supposed
to be the MCC range which contains the slew rate registers, not the slew
rate register base. The Linux driver then accesses slew rate register
with hard-coded offset (0xa000).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230302155255.857065-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Enable yamllint to check the preferred commenting style of requiring a
space after a comment character '#'. Fix the cases in the tree which
have a warning with this enabled. Most cases just need a space after the
'#'. A couple of cases with comments which were not intended to be
comments are revealed. Those were in ti,sa2ul.yaml, ti,cal.yaml, and
brcm,bcmgenet.yaml.
Acked-by: Jakub Kicinski <kuba@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # drm/msm
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20230303214223.49451-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
SPI and I2C bus node names are expected to be "spi" or "i2c",
respectively, with nothing else, a unit-address, or a '-N' index. A
pattern of 'spi0' or 'i2c0' or similar has crept in. Fix all these
cases. Mostly scripted with the following commands:
git grep -l '\si2c[0-9] {' Documentation/devicetree/ | xargs sed -i -e 's/i2c[0-9] {/i2c {/'
git grep -l '\sspi[0-9] {' Documentation/devicetree/ | xargs sed -i -e 's/spi[0-9] {/spi {/'
With this, a few errors in examples were exposed and fixed.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for the microchip,mcp251xfd.yaml
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> # for power-supply
Acked-by: Wolfram Sang <wsa@kernel.org>
Acked-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230228215433.3944508-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
DT core:
- Add node lifecycle unit tests
- Add of_property_present() helper aligned with fwnode API
- Print more information on reserved regions on boot
- Update dtc to upstream v1.6.1-66-gabbd523bae6e
- Use strscpy() to instead of strncpy() in DT core
- Add option for schema validation on %.dtb targets
Bindings:
- Add/fix support for listing multiple patterns in DT_SCHEMA_FILES
- Rework external memory controller/bus bindings to properly support
controller specific child node properties
- Convert loongson,ls1x-intc, fcs,fusb302, sil,sii8620, Rockchip RK3399
PCIe, Synquacer I2C, and Synquacer EXIU bindings to DT schema format
- Add RiscV SBI PMU event mapping binding
- Add missing contraints on Arm SCMI child node allowed properties
- Add a bunch of missing Socionext UniPhier glue block bindings and
example fixes
- Various fixes for duplicate or conflicting type definitions on DT
properties
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Merge tag 'devicetree-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT core:
- Add node lifecycle unit tests
- Add of_property_present() helper aligned with fwnode API
- Print more information on reserved regions on boot
- Update dtc to upstream v1.6.1-66-gabbd523bae6e
- Use strscpy() to instead of strncpy() in DT core
- Add option for schema validation on %.dtb targets
Bindings:
- Add/fix support for listing multiple patterns in DT_SCHEMA_FILES
- Rework external memory controller/bus bindings to properly support
controller specific child node properties
- Convert loongson,ls1x-intc, fcs,fusb302, sil,sii8620, Rockchip
RK3399 PCIe, Synquacer I2C, and Synquacer EXIU bindings to DT
schema format
- Add RiscV SBI PMU event mapping binding
- Add missing contraints on Arm SCMI child node allowed properties
- Add a bunch of missing Socionext UniPhier glue block bindings and
example fixes
- Various fixes for duplicate or conflicting type definitions on DT
properties"
* tag 'devicetree-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (66 commits)
dt-bindings: regulator: Add mps,mpq7932 power-management IC
of: dynamic: Fix spelling mistake "kojbect" -> "kobject"
dt-bindings: drop Sagar Kadam from SiFive binding maintainership
dt-bindings: sram: qcom,imem: document sm8450
dt-bindings: interrupt-controller: convert loongson,ls1x-intc.txt to json-schema
dt-bindings: arm: Add Cortex-A715 and X3
of: dynamic: add lifecycle docbook info to node creation functions
of: add consistency check to of_node_release()
of: do not use "%pOF" printk format on node with refcount of zero
of: unittest: add node lifecycle tests
of: update kconfig unittest help
of: add processing of EXPECT_NOT to of_unittest_expect
of: prepare to add processing of EXPECT_NOT to of_unittest_expect
of: Use preferred of_property_read_* functions
of: Use of_property_present() helper
of: Add of_property_present() helper
of: reserved_mem: Use proper binary prefix
dt-bindings: Fix multi pattern support in DT_SCHEMA_FILES
of: reserved-mem: print out reserved-mem details during boot
dt-bindings: serial: restrict possible child node names
...
Several minor cleanups and fixes on Qualcomm pin controller Devicetree
bindings - add missing input-disable, correct GPIO pin name patterns in
bindings, correct number of GPIOs in gpio-ranges property.
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Merge tag 'qcom-pinctrl-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel
Qualcomm pinctrl Devicetree bindings changes for v6.3, part two
Several minor cleanups and fixes on Qualcomm pin controller Devicetree
bindings - add missing input-disable, correct GPIO pin name patterns in
bindings, correct number of GPIOs in gpio-ranges property.
Add bindings for the MT7981 pinctrl driver. As MT7981 has most features
in common with MT7986 (but has a different layout in terms on pinctrl
and clocks), the existing mediatek,mt7986-pinctrl.yaml was used as an
example to create a similar document covering MT7981.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/3f0fd0becc338eef66caeb7244c3c432b8d1ef7a.1674693008.git.daniel@makrotopia.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Mark gpio sub nodes of pinctrl as deprecated.
Gpio nodes are now placed in the root of the device tree.
The relation to pinctrl is now described with the
"gpio-ranges" property.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/137b56f0-8e86-f705-4ba7-d5dfe3c0b477@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The MSM8909 TLMM pin controller has GPIOs 0-112, so narrow the pattern
and gpio-ranges in the example.
Fixes: c249ec7ba1 ("dt-bindings: pinctrl: Add DT schema for qcom,msm8909-tlmm")
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230202104452.299048-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The MSM8226 TLMM pin controller has GPIOs 0-116, so correct the pattern
to bring back missing 107-109.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Luca Weiss <luca@z3ntu.xyz>
Link: https://lore.kernel.org/r/20230202104452.299048-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The SM8350 HDK8350 board uses input-disable property, so allow it:
sm8350-hdk.dtb: pinctrl@f100000: lt9611-state: 'oneOf' conditional failed, one must be fixed:
...
'input-disable' does not match any of the regexes: 'pinctrl-[0-9]+'
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230201154321.276419-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Set of cleanups and fixes for Qualcomm pin controller bindings, to match
existing DTS and correct the schema.
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Merge tag 'qcom-pinctrl-6.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel
Qualcomm pinctrl Devicetree bindings changes for v6.3
Set of cleanups and fixes for Qualcomm pin controller bindings, to match
existing DTS and correct the schema.
The child node name patterns in Mediatek pinctrl bindings don't match
reality. I don't know where '-[0-9]+$' came from, but I don't see any nodes
with a matching pattern. Also, patterns such as 'pins' or 'mux' are
ambiguous because any prefix or suffix is allowed. If that's desired, it
should be explicit.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230120020536.3229300-1-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Just 'mpp' is a bit ambiguous for a pattern as it allows any prefix or
suffix. Change the node name pattern to "-pins$" to align with other
Qualcomm pinctrl bindings.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230120165103.1278852-1-robh@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Not every function can be muxed to a group. Add proper binding which
documents which function can be muxed to a group or set of groups.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20221231160849.40544-7-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Not every function can be muxed to a group. Add proper binding which
documents which function can be muxed to a group or set of groups.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20221231160849.40544-6-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Not every function can be muxed to a group. Add proper binding which
documents which function can be muxed to a group or set of groups.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20221231160849.40544-5-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Not every function can be muxed to a group. Add proper binding which
documents which function can be muxed to a group or set of groups.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20221231160849.40544-4-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Not every function can be muxed to a group. Add proper binding which
documents which function can be muxed to a group or set of groups.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20221231160849.40544-3-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Almost all Qualcomm SoC Top Level Mode Multiplexers come with only
summary interrupt. SM6350 is different because downstream and upstream
DTS have nine of the interrupts. Allow such variation.
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221230135645.56401-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Allow gpio-line-names property (quite commonly used) and constrain
gpio-reserved-ranges:
sm8350-sony-xperia-sagami-pdx215.dtb: pinctrl@f100000: 'gpio-line-names' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221230135645.56401-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Allow bias-bus-hold and input-enable properties (already used in
SC8280XP LPASS LPI nodes):
sa8540p-ride.dtb: pinctrl@33c0000: tx-swr-default-state: 'oneOf' conditional failed, one must be fixed:
'pins' is a required property
'function' is a required property
'clk-pins', 'data-pins' do not match any of the regexes: 'pinctrl-[0-9]+'
'bias-bus-hold' does not match any of the regexes: 'pinctrl-[0-9]+'
Link: https://lore.kernel.org/r/20221230135645.56401-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
SC8280XP LPASS LPI pin controller has GPIO 0-18:
sa8540p-ride.dtb: pinctrl@33c0000: tx-swr-default-state: 'oneOf' conditional failed, one must be fixed:
'pins' is a required property
'function' is a required property
'clk-pins', 'data-pins' do not match any of the regexes: 'pinctrl-[0-9]+'
'bias-bus-hold' does not match any of the regexes: 'pinctrl-[0-9]+'
'gpio2' does not match '^gpio([0-1]|1[0-8])$'
Fixes: 958bb025f5 ("dt-bindings: pinctrl: qcom: Add sc8280xp lpass lpi pinctrl bindings")
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221230135645.56401-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Allow bias-bus-hold and input-enable properties (already used in SM8450):
sm8450-qrd.dtb: pinctrl@3440000: dmic02-default-state: 'oneOf' conditional failed, one must be fixed:
'pins' is a required property
'function' is a required property
'clk-pins', 'data-pins' do not match any of the regexes: 'pinctrl-[0-9]+'
'input-enable' does not match any of the regexes: 'pinctrl-[0-9]+'
Compact the properties which are just set to true for readability.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221222161420.172824-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The SM8450 has GPIOs from 0 to 209, so 210 in total:
sm8450-sony-xperia-nagara-pdx223.dtb: pinctrl@f100000: gpio-line-names:
['NC', 'NC', 'NC', 'NC', 'WLC_I2C_SDA', 'WLC_I2C_SCL', ...
'APPS_I2C_0_SDA', 'APPS_I2C_0_SCL', 'CCI_I2C3_SDA', 'CCI_I2C3_SCL'] is too long
Fixes: 9779ed30f9 ("dt-bindings: pinctrl: qcom,sm8450-pinctrl: add gpio-line-names")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221223132226.81340-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Document the general purpose clock functions that are found on MSM8226.
Signed-off-by: Matti Lehtimäki <matti.lehtimaki@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230106114403.275865-2-matti.lehtimaki@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The i.MX8MM/N/P/Q IOMUXC schemas are basically the same, it does not to
have four schemas for almost the same binding.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230104021430.3503497-1-peng.fan@oss.nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add device tree binding Documentation details for Qualcomm SM8550
TLMM device
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221230203637.2539900-2-abel.vesa@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221215213206.56666-2-biju.das.jz@bp.renesas.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Drop parent node of the pinctrl as it is not directly necessary, and
add more examples, that is "groups", "function", and a child node to set
pin attributes, to express this pinctrl node in detail.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20221213082449.2721-4-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
The Devicetree bindings document does not have to say in the title that
it is a "Devicetree binding" or a "schema", but instead just describe
the hardware.
Manual updates to various binding titles, including capitalizing them.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org> # opp
Link: https://lore.kernel.org/r/20221216163815.522628-10-krzysztof.kozlowski@linaro.org
[robh: add trivial-devices.yaml and net/can/microchip,mcp251xfd.yaml]
Signed-off-by: Rob Herring <robh@kernel.org>
The Devicetree bindings document does not have to say in the title that
it is a "binding", but instead just describe the hardware.
Drop trailing "bindings" in various forms (also with trailing full
stop):
find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
-not -name 'trivial-devices.yaml' \
-exec sed -i -e 's/^title: \(.*\) [bB]indings\?\.\?$/title: \1/' {} \;
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Matti Vaittinen <mazziesaccount@gmail.com> # ROHM
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> # media
Acked-by: Sebastian Reichel <sre@kernel.org> # power
Acked-by: Viresh Kumar <viresh.kumar@linaro.org> # cpufreq
Link: https://lore.kernel.org/r/20221216163815.522628-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
The Devicetree bindings document does not have to say in the title that
it is a "Devicetree binding", but instead just describe the hardware.
Drop trailing "Devicetree bindings" in various forms (also with
trailing full stop):
find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
-not -name 'trivial-devices.yaml' \
-exec sed -i -e 's/^title: \(.*\) [dD]evice[ -]\?[tT]ree [bB]indings\?\.\?$/title: \1/' {} \;
find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
-not -name 'trivial-devices.yaml' \
-exec sed -i -e 's/^title: \(.*\) [dD]evice[ -]\?[nN]ode [bB]indings\?\.\?$/title: \1/' {} \;
find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
-not -name 'trivial-devices.yaml' \
-exec sed -i -e 's/^title: \(.*\) [dD][tT] [bB]indings\?\.\?$/title: \1/' {} \;
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # IIO
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> # media
Acked-by: Sebastian Reichel <sre@kernel.org> # power
Link: https://lore.kernel.org/r/20221216163815.522628-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
Core changes:
- Minor but nice and important documentation clean-ups.
New drivers:
- New subdriver for the Qualcomm SDM670 SoC.
- New subdriver for the Intel Moorefield SoC.
- New trivial support for the NXP Freescale i.MXRT1170 SoC.
Other changes and improvements
- A major clean-up of the Qualcomm pin control device tree bindings
by Krzysztof.
- A major header clean-up by Andy.
- Some immutable irqchip clean-up for the Actions Semiconductor
and Nuvoton drivers.
- GPIO helpers for The Cypress cy8c95x0 driver.
- Bias handling in the Mediatek MT7986 driver.
- Remove the unused pins-are-numbered concept that never flew.
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Merge tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"The two large chunks is the header clean-up from Andy and the Qualcomm
DT bindings clean-up from Krzysztof. Each which could give rise to
conflicts, but I haven't seen any.
The YAML conversions happening around the device tree is the biggest
item in the series and is the result of Rob Herrings ambition to
autovalidate these trees against strict schemas and it is paying off
in lots of bugs found and ever prettier device trees. Sooner or later
the transition will be complete, Krzysztof is fixing up all of the
Qualcomm stuff, which is pretty voluminous.
Core changes:
- minor but nice and important documentation clean-ups
New drivers:
- subdriver for the Qualcomm SDM670 SoC
- subdriver for the Intel Moorefield SoC
- trivial support for the NXP Freescale i.MXRT1170 SoC
Other changes and improvements
- major clean-up of the Qualcomm pin control device tree bindings by
Krzysztof
- major header clean-up by Andy
- some immutable irqchip clean-up for the Actions Semiconductor and
Nuvoton drivers
- GPIO helpers for The Cypress cy8c95x0 driver
- bias handling in the Mediatek MT7986 driver
- remove the unused pins-are-numbered concept that never flew"
* tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (231 commits)
pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions()
dt-bindings: pinctrl: st,stm32: Deprecate pins-are-numbered
dt-bindings: pinctrl: mediatek,mt65xx: Deprecate pins-are-numbered
pinctrl: stm32: Remove check for pins-are-numbered
pinctrl: mediatek: common: Remove check for pins-are-numbered
pinctrl: qcom: remove duplicate included header files
pinctrl: sunxi: d1: Add CAN bus pinmuxes
pinctrl: loongson2: Fix some const correctness
pinctrl: pinconf-generic: add missing of_node_put()
pinctrl: intel: Enumerate PWM device when community has a capability
pwm: lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()
pwm: lpss: Allow other drivers to enable PWM LPSS
pwm: lpss: Include headers we are the direct user of
pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
pwm: Add a stub for devm_pwmchip_add()
pinctrl: k210: call of_node_put()
pinctrl: starfive: Use existing variable gpio
dt-bindings: pinctrl: semtech,sx150xq: fix match patterns for 16 GPIOs matching
pinconf-generic: fix style issues in pin_config_param doc
pinctrl: pinctrl-loongson2: fix Kconfig dependency
...
The devicetree changes contain exactly 1000 non-merge changesets,
including a number of new arm64 SoC variants from Qualcomm and Apple,
as well as the Renesas r9a07g043f/u chip in both arm64 and riscv variants
While we have occasionally merged support for non-arm SoCs in the past,
this is now the normal path for riscv devicetree files.
The most notable changes, by SoC platform, are:
- The Apple T6000 (M1 Pro), T6001 (M1 Max) and T6002 (M2 Ultra)
chips now have initial support. This is particularly nice as I am
typing this on a T6002 Mac Studio with only a small number of driver
patches.
- Qualcomm MSM8996 Pro (Snapdragon 821), SM6115 (Snapdragon 662), SM4250
(Snapdragon 460), SM6375 (Snapdragon 695), SDM670 (Snapdragon 670),
MSM8976 (Snapdragon 652) and MSM8956 (Snapdragon 650) are all mobile
phone chips that are closely related to others we already support.
Adding those helps support more phones and we add several models
from Sony (Xperia 10 IV, 5 IV, X, and X compact), OnePlus (One, 3,
3T, and Nord N100), Xiaomi (Poco F1, Mi6), Huawei (Watch) and Google
(Pixel 3a). There are also new variants of the Herobrine and Trogdor
chromebook motherboards. SA8540P is an automotive SoC used in the
Qdrive-3 development platform
- Rockchips gains no new SoC variants, but a lot of new boards:
three mobile gaming systems based on RK3326 Odroid-Go/rg351 family,
two more Anbernic gaming systems based on RK3566 and a number of
other RK356x based single-board computers.
- Renesas RZ/G2UL (r9a07g043) was already supported for arm64, but as
the newly added RZ/Five is based on the same design, this now gets
reorganized in order to share most of the dts description between
the two and add the RZ/Five SMARC EVK board support.
Aside from that, there are the usual changes all over the tree:
- New boards on other platforms contain two ASpeed BMC users, two
Broadcom based Wifi routers, Zyxel NSA310S NAS, the i.MX6 based Kobo
Aura2 ebook reader, two i.MX8 based development boards, two Uniphier
Pro5 development boards, the STM32MP1 testbench board from DHCOR,
the TI K3 based BeagleBone AI-64 board, and the Mediatek Helio X10
based Sony Xperia M5 phone.
- The Starfive JH7100 source gets reorganized in order to support the
VisionFive V1 board.
- Minor updates and cleanups for Intel SoCFPGA, Marvell PXA168,
TI, ST, NXP, Apple, Broadcom, Juno, Marvell MVEBU, at91, nuvoton,
Tegra, Mediatek, Renesas, Hisilicon, Allwinner, Samsung, ux500,
spear, ... The treewide cleanups now have a lot of fixes for cache
nodes and other binding violoations.
- Somewhat larger sets of reworks for NVIDIA Tegra, Qualcomm
and Renesas platforms, adding a lot more on-chip device support
- A rework of the way that DTB overlays are built.
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Merge tag 'soc-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC DT updates from Arnd Bergmann:
"The devicetree changes contain exactly 1000 non-merge changesets,
including a number of new arm64 SoC variants from Qualcomm and Apple,
as well as the Renesas r9a07g043f/u chip in both arm64 and riscv
variants.
While we have occasionally merged support for non-arm SoCs in the
past, this is now the normal path for riscv devicetree files.
The most notable changes, by SoC platform, are:
- The Apple T6000 (M1 Pro), T6001 (M1 Max) and T6002 (M1 Ultra) chips
now have initial support. This is particularly nice as I am typing
this on a T6002 Mac Studio with only a small number of driver
patches.
- Qualcomm MSM8996 Pro (Snapdragon 821), SM6115 (Snapdragon 662),
SM4250 (Snapdragon 460), SM6375 (Snapdragon 695), SDM670
(Snapdragon 670), MSM8976 (Snapdragon 652) and MSM8956 (Snapdragon
650) are all mobile phone chips that are closely related to others
we already support.
Adding those helps support more phones and we add several models
from Sony (Xperia 10 IV, 5 IV, X, and X compact), OnePlus (One, 3,
3T, and Nord N100), Xiaomi (Poco F1, Mi6), Huawei (Watch) and
Google (Pixel 3a).
There are also new variants of the Herobrine and Trogdor chromebook
motherboards. SA8540P is an automotive SoC used in the Qdrive-3
development platform
- Rockchips gains no new SoC variants, but a lot of new boards: three
mobile gaming systems based on RK3326 Odroid-Go/rg351 family, two
more Anbernic gaming systems based on RK3566 and a number of other
RK356x based single-board computers.
- Renesas RZ/G2UL (r9a07g043) was already supported for arm64, but as
the newly added RZ/Five is based on the same design, this now gets
reorganized in order to share most of the dts description between
the two and add the RZ/Five SMARC EVK board support.
Aside from that, there are the usual changes all over the tree:
- New boards on other platforms contain two ASpeed BMC users, two
Broadcom based Wifi routers, Zyxel NSA310S NAS, the i.MX6 based
Kobo Aura2 ebook reader, two i.MX8 based development boards, two
Uniphier Pro5 development boards, the STM32MP1 testbench board from
DHCOR, the TI K3 based BeagleBone AI-64 board, and the Mediatek
Helio X10 based Sony Xperia M5 phone.
- The Starfive JH7100 source gets reorganized in order to support the
VisionFive V1 board.
- Minor updates and cleanups for Intel SoCFPGA, Marvell PXA168, TI,
ST, NXP, Apple, Broadcom, Juno, Marvell MVEBU, at91, nuvoton,
Tegra, Mediatek, Renesas, Hisilicon, Allwinner, Samsung, ux500,
spear, ... The treewide cleanups now have a lot of fixes for cache
nodes and other binding violoations.
- Somewhat larger sets of reworks for NVIDIA Tegra, Qualcomm and
Renesas platforms, adding a lot more on-chip device support
- A rework of the way that DTB overlays are built"
* tag 'soc-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (979 commits)
arm64: dts: apple: t6002: Fix GPU power domains
arm64: dts: apple: t600x-pmgr: Fix search & replace typo
arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes
arm64: dts: apple: Rename dart-sio* to sio-dart*
arch: arm64: apple: t600x: Use standard "iommu" node name
arch: arm64: apple: t8103: Use standard "iommu" node name
ARM: dts: socfpga: Fix pca9548 i2c-mux node name
dt-bindings: iio: adc: qcom,spmi-vadc: fix PM8350 define
dt-bindings: iio: adc: qcom,spmi-vadc: extend example
arm64: dts: qcom: sc8280xp: fix UFS DMA coherency
arm64: dts: qcom: sc7280: Add DT for sc7280-herobrine-zombie
arm64: dts: qcom: sm8250-sony-xperia-edo: fix no-mmc property for SDHCI
arm64: dts: qcom: sdm845-sony-xperia-tama: fix no-mmc property for SDHCI
arm64: dts: qcom: sda660-inforce-ifc6560: fix no-mmc property for SDHCI
arm64: dts: qcom: sa8155p-adp: fix no-mmc property for SDHCI
arm64: dts: qcom: qrb5165-rb: fix no-mmc property for SDHCI
arm64: dts: qcom: sm8450: align MMC node names with dtschema
arm64: dts: qcom: sc7180-trogdor: use generic node names
arm64: dts: qcom: sm8450-hdk: add sound support
arm64: dts: qcom: sm8450: add Soundwire and LPASS
...
Make pins-are-numbered optional and deprecate it
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221129023401.278780-4-bero@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The current pattern for SX1503 and SX1509Q with 16 GPIOs only matches
"gpio0", "gpio1", and "gpio5" instead of "gpio0" to "gpio15" included.
Fix these patterns to match the whole 16 GPIO line names.
Fixes: 29c10bcec5 ("dt-bindings: pinctrl: convert semtech,sx150xq bindings to dt-schema")
Reported-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20221121-sx150xq_bindings_fixup-v1-0-e754f183b611@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tegra194 has two separate instances of the pin controller, one called
AON (in the always-on domain) and another called "main". Instead of
treating them as a single pin controller, split them up into two
separate controllers. Doing so allows the mapping between the pinmux and
GPIO controllers to be trivial identity mappings and more cleanly
separates the AON from the main IP blocks.
Note that while this changes the DT node in an incompatible way, this
doesn't have any practical implications for backwards-compatibility. The
reason for this is that device trees have only reconfigured a very
narrow subset of pins of the main controller, so the new driver will
remain backwards-compatible with old device trees.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra pinmux controller bindings from the free-form
text format to json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the Loongson-2 pinctrl binding with DT schema format using
json-schema.
Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Link: https://lore.kernel.org/r/20221114024942.8111-2-zhuyinbo@loongson.cn
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Apparently RK3588 pinctrl has 13 different device functions, but dt-validate
only checks for pin configuration being referenced so I did not notice.
Fixes: ed1f77b783 ("dt-bindings: pinctrl: rockchip: increase max amount of device functions")
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20221021172012.87954-1-sebastian.reichel@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This converts the Semtech SX150Xq bindings to dt-schemas, add necessary
bindings documentation to cover all differences between HW variants
and current bindings usage.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221005-mdm9615-sx1509q-yaml-v3-0-e8b349eb1900@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Convert Qualcomm MSM8976 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Changes during conversion: update the list of non-mux pins (like sdc1)
to match Linux driver.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20221110085230.15108-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Convert Qualcomm MSM8960 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221109105140.48196-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Convert Qualcomm IPQ8074 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221108142357.67202-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Convert Qualcomm MSM8660 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107185931.22075-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Since the bias-pull-{up,down} attribute already defines in pinctrl driver
of mediatek MT7986 SoC, this patch updates bindings to support mediatek
common bias-pull* function.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221106080114.7426-4-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix mmc and uart pins after uart splitting.
Some pinmux pins of the mt7986 pinctrl driver is composed of multiple
pinctrl groups, the original binding only allows one pinctrl group
per dts node, this patch sets "maxItems" for these groups and add new
examples to the binding documentation.
Fixes: 65916a1ca9 ("dt-bindings: pinctrl: update bindings for MT7986 SoC")
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221106080114.7426-3-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Clarify the meaning of sysirq to avoid confusion.
Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221028153505.23741-7-y.oudjana@protonmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The document currently states a maximum of 1 interrupt, but the DT
has 2 specified causing a dtbs_check error. Replace the maximum limit
with a minimum and add per-interrupt descriptions to pass the check.
Fixes: 81557a7156 ("dt-bindings: pinctrl: Add MediaTek MT6795 pinctrl bindings")
Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221028153505.23741-6-y.oudjana@protonmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Combine MT6797 pin controller document into MT6779 one. reg and
reg-names property constraints are set using conditionals.
A conditional is also used to make interrupt-related properties
required on the MT6779 pin controller only, since the MT6797
controller doesn't support interrupts (or not yet, at least).
drive-strength and slew-rate properties which weren't described
in the MT6779 document before are brought in from the MT6797 one.
Both pin controllers share a common driver core so they should
both support these properties.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221028153505.23741-5-y.oudjana@protonmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pin controller can function without specifying gpio-ranges so remove
it from required properties. This is also done in preparation for adding
other pin controllers which currently don't have the gpio-ranges property
defined where they are used in DTS. This allows dtbs_check to pass on
those device trees.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221028153505.23741-4-y.oudjana@protonmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The current description mentions having to put the pin controller
node under a syscon node, but this is not the case in the current
MT6779 device tree. This is not actually needed, so replace the
current description with something more generic that describes
the use of the hardware block.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221028153505.23741-3-y.oudjana@protonmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Convert Qualcomm QCS404 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Changes during conversion: add sdc1_rclk pins (used in qcs404-evb.dtsi).
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221104161131.57719-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Convert Qualcomm MSM8916 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221024002356.28261-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Big set of refactoring and improving Qualcomm pin controller bindings:
1. Convert several bindings from TXT to DT schema format: MDM9615,
MSM8974, MSM8994, MSM8996, MSM8998, SC7180, SDM630, SDM845, SM8150.
2. Refactor existing DT schema bindings to be consistent and similar to
each other, remove unneeded pieces (provided by common bindings) and
unify the style.
2. Fix matching of the existing DT schema bindings, so they properly
validate the DTS. When looking for pin configuration (children
nodes), be specific and expect "state" or "pins" suffixes (depending
on the nesting. This allows the schema later to properly parse also
GPIO hogs, although it is not yet implemented. The changes require
aligning the DTS to new layout, but it does not break any
compatibility.
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Merge tag 'qcom-pinctrl-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel
Qualcomm pinctrl Devicetree bindings changes for v6.2
Big set of refactoring and improving Qualcomm pin controller bindings:
1. Convert several bindings from TXT to DT schema format: MDM9615,
MSM8974, MSM8994, MSM8996, MSM8998, SC7180, SDM630, SDM845, SM8150.
2. Refactor existing DT schema bindings to be consistent and similar to
each other, remove unneeded pieces (provided by common bindings) and
unify the style.
2. Fix matching of the existing DT schema bindings, so they properly
validate the DTS. When looking for pin configuration (children
nodes), be specific and expect "state" or "pins" suffixes (depending
on the nesting. This allows the schema later to properly parse also
GPIO hogs, although it is not yet implemented. The changes require
aligning the DTS to new layout, but it does not break any
compatibility.
Convert Qualcomm SC7180 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20221019001351.1630089-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Convert Qualcomm MSM8974 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221017012225.8579-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
If minItems are missing, they are implicitly equal to maxItems.
Dropping redundant minItems simplifies a bit the binding.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Iskren Chernev <iskren.chernev@gmail.com>
Link: https://lore.kernel.org/r/20221016173625.53769-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Convert Qualcomm MSM8994 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221018155450.39816-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Convert Qualcomm MSM8996 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221018155721.47140-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Convert Qualcomm MSM8998 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221017234653.55506-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Convert Qualcomm SM8150 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221018160128.51851-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description, because the field should describe the
hardware.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-34-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently and drop redundant
quotes.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-33-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), drop redundant minItems, use double quotes
consistently and drop redundant quotes.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-32-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently and drop redundant
quotes.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-31-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently and drop redundant
quotes.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-30-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently, drop redundant
quotes and rename file to match compatible (to match coding convention).
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-29-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently, drop redundant
quotes and rename file to match compatible (to match coding convention).
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-28-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), drop redundant minItems, use double quotes
consistently and drop redundant quotes.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-27-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently and drop redundant
quotes.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-26-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently, drop redundant
quotes and rename file to match compatible (to match coding convention).
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-25-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), drop redundant minItems, use double quotes
consistently, drop redundant quotes and rename file to match compatible
(to match coding convention).
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-24-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently, drop redundant
quotes and rename file to match compatible (to match coding convention).
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Iskren Chernev <iskren.chernev@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-23-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently, drop redundant
quotes and rename file to match compatible (to match coding convention).
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-22-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently, drop redundant quotes
and rename file to match compatible (to match coding convention).
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-21-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently, drop redundant
quotes and rename file to match compatible (to match coding
convention).
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-20-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently, drop redundant
quotes and rename file to match compatible (to match coding convention).
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-19-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently and drop redundant
quotes.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephan Gerhold <stephan@gerhold.net>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-18-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently, drop redundant
quotes and rename file to match compatible (to match coding
convention).
Acked-by: Stephan Gerhold <stephan@gerhold.net>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-17-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The common Qualcomm TLMM pin controller schema already brings
requirement of function for GPIO pins.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-16-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The common Qualcomm TLMM pin controller schema already brings
requirement of function for GPIO pins.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-15-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reference common Qualcomm TLMM pin controller schema, to bring common
properties, other pinctrl schemas and additional checks, like function
required only for GPIOs.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-13-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The common Qualcomm TLMM pin controller schema already brings
requirement of function for GPIO pins.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-12-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The common Qualcomm TLMM pin controller schema already brings
requirement of function for GPIO pins.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-10-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The common Qualcomm TLMM pin controller schema already brings
requirement of function for GPIO pins.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reference common Qualcomm TLMM pin controller schema, to bring common
properties, other pinctrl schemas and additional checks, like function
required only for GPIOs.
Reviewed-by: Iskren Chernev <iskren.chernev@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The common Qualcomm TLMM pin controller schema already brings
requirement of function for GPIO pins.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The common Qualcomm TLMM pin controller schema already brings
requirement of function for GPIO pins.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The common Qualcomm TLMM pin controller schema for pin mux and config
already brings requirement of function for gpio pins and the definition
of drive-strength.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221016172212.49105-18-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The SC7280 pinctrl driver supports bias-bus-hold and input-enable, and
DTS already use it (sc7280-idp).
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221016172212.49105-17-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
SC7280 has 175 GPIOs (gpio0-174), so correct size of gpio-line-names and
narrow the pattern for matching pin names.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221016172212.49105-16-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The SM8250 pinctrl driver supports input-enable and DTS already use it
(sm8250-sony-xperia-edo-pdx203).
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221016172212.49105-15-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The TLMM pin controller follows generic pin-controller bindings, so
should have subnodes with '-state' and '-pins'. Otherwise the subnodes
(level one and two) are not properly matched. This method also unifies
the bindings with other Qualcomm TLMM and LPASS pinctrl bindings.
The change causes indentation decrement, so the diff-hunk looks big, but
there are no functional changes in the subnode "properties" section.
The only difference there is removal of blank lines between common GPIO
pinconf properties.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221016172212.49105-14-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The common Qualcomm TLMM pin controller schema for pin mux and config
already brings requirement of function for gpio pins and the definition
of drive-strength.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221016172212.49105-13-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Document common GPIO properties (gpio-reserved-ranges and
gpio-line-names), already used on qrb5165-rb5 board.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221016172212.49105-12-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This reverts commit 133ad0d9af.
On systems with older PMUFW (Xilinx ZynqMP Platform Management Firmware)
using these pinctrl properties can cause system hang because there is
missing feature autodetection.
When this feature is implemented, support for these two properties should
bring back.
Cc: stable@vger.kernel.org
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221017130303.21746-3-sai.krishna.potthuri@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Convert Qualcomm SDM630 and SDM660 pin controller bindings to DT schema.
Keep the parsing of pin configuration subnodes consistent with other
Qualcomm schemas (children named with '-state' suffix, their children
with '-pins').
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221011190231.76784-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Convert Qualcomm SDM845 pin controller bindings to DT schema. Keep
the parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220930200529.331223-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Convert the MDM9515 pinctrl bindings to dt-schema.
Keep the parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, optional children with '-pins').
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221005-mdm9615-pinctrl-yaml-v2-1-639fe67a04be@linaro.org
[krzk: drop function from required]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
