The CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC has five
interrupts:
- image_conv: image_conv irq
- axi_mst_err: AXI master error level irq
- vd_addr_wend: Video data AXI master addr 0 write end irq
- sd_addr_wend: Statistics data AXI master addr 0 write end irq
- vsd_addr_wend: Video statistics data AXI master addr 0 write end irq
This IP has only one input port 'port@1' similar to the RZ/G2UL CRU.
Document the CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://lore.kernel.org/r/20250411170624.472257-4-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Document the CRU IP found in Renesas RZ/G2UL SoC.
The CRU block on the RZ/G2UL SoC is identical to one found on the
RZ/G2L SoC, but it does not support parallel input.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240605154115.263447-3-biju.das.jz@bp.renesas.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
