Add binding documentation for the Xilinx System Management Wizard. The
Xilinx System Management Wizard is a AXI frontend for the Xilinx System
Monitor found in the UltraScale and UltraScale+ FPGAs.
The System Monitor is the equivalent to the Xilinx XADC found in their
previous generation of FPGAs and their external and internal interfaces are
very similar. For this reason the share the same binding documentation. But
since they are not 100% compatible and software will have to know about the
differences they use a different compatible string.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20200922134624.13191-1-lars@metafoo.de
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
'interrupt-parent' is often documented as part of define bindings, but
it is really outside the scope of a device binding. It's never required
in a given node as it is often inherited from a parent node. Or it can
be implicit if a parent node is an 'interrupt-controller' node. So
remove it from all the binding files.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
This patch fix multiple words such as "the the" and "which which"
in Documentation/devicetree.
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx.
The XADC has a DRP interface for communication. Currently two different
frontends for the DRP interface exist. One that is only available on the ZYNQ
family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
on all series 7 platforms and is a softmacro with a AXI interface. This binding
document describes the bindings for both of them since the bindings are very
similar.
Each of them needs:
* A address range where the registers are mapped
* An interrupt number for the device interrupt
* A clock. For the the ZYNQ hardmacro interface this is the modules PCAP
clock, for the AXI softmacro it is the AXI bus interface clock.
Additionally the bindings specify whether an external multiplexer is used and in
which mode it is used. The devicetree bindings also describe which external
channels are connected and in which configuration.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
