The I2C controllers found on Apple A7-A11, T2 SoCs are compatible with
the existing driver so add their per-SoC compatibles.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Reviewed-by: Sven Peter <sven@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20250610-i2c-no-t2-v2-1-a5a71080fba9@gmail.com
The I2C controllers in most Rockchip SoCs are part of power domains that
are always powered on, i.e. PD_BUS or PD_PMU. These always powered
on power domains have typically not been described in the device tree.
Because these power domains have been left out of the device tree there
has not been any real need to properly describe the I2C controllers
power domain.
On RK3528 the I2C controllers are spread out among the described
PD_RKVENC, PD_VO and PD_VPU power domains. However, one I2C controller
belong to an undescribed always powered on power domain.
Add support to describe an optional power-domains for the I2C
controllers in Rockchip SoCs.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20250723085654.2273324-3-jonas@kwiboo.se
Allow clocks property to fix below CHECK_DTB warnings:
arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dtb: i2c@300 (nxp,pnx-i2c): Unevaluated properties are not allowed ('clocks' was unexpected)
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20250624200444.2514331-1-Frank.Li@nxp.com
Document support for the I2C Bus Interface (RIIC) found on the Renesas
RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs.
The RIIC IP on these parts is similar to that on RZ/V2H(P) but supports
only four interrupts (including a combined error/event), lacks FM+ mode,
and does not require reset. Introduce a new compatible string
`renesas,riic-r9a09g077` for RZ/T2H and use it as a fallback for RZ/N2H.
Unlike earlier SoCs that use eight distinct interrupts, the RZ/T2H uses
only four. Update the binding schema to reflect this interrupt layout
and skip the `resets` property check, as it is not required on these SoCs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20250625104526.101004-3-prabhakar.mahadev-lad.rj@bp.renesas.com
In preparation for adding more validation checks, move the `$ref` for
'i2c-controller.yaml' to the end of the file. Also, relocate the
conditional check for 'resets' into the 'allOf' block.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20250625104526.101004-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Lists should have fixed amount if items, so add missing constraint to
the 'reg' property (only one address space entry).
Fixes: c5eda03330 ("dt-bindings: i2c: Add Realtek RTL I2C Controller")
Cc: <stable@vger.kernel.org> # v6.13+
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20250702061530.6940-2-krzysztof.kozlowski@linaro.org
Specify the properties which are essential and which are not for the
Tegra I2C driver to function correctly. This was not added correctly when
the TXT binding was converted to yaml. All the existing DT nodes have
these properties already and hence this does not break the ABI.
dmas and dma-names which were specified as a must in the TXT binding
is now made optional since the driver can work in PIO mode if dmas are
missing.
Fixes: f10a9b722f ("dt-bindings: i2c: tegra: Convert to json-schema”)
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Cc: <stable@vger.kernel.org> # v5.17+
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Andi Shyti <andi@smida.it>
Link: https://lore.kernel.org/r/20250603153022.39434-1-akhilrajeev@nvidia.com
Rewrite the textual description for the WonderMedia I2C controller
as YAML schema, and switch the filename to follow the compatible
string.
The controller only supports two bus speeds (100kHz and 400kHz)
so restrict clock-frequency values accordingly.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20250506-vt8500-i2c-binding-v3-1-401c3e090a88@gmail.com
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Document I2C controllers integrated in RK3528, which are compatible with
the RK3399 variant.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20250417120118.17610-4-ziyao@disroot.org
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Document support for the I2C Bus Interface (RIIC) found on the Renesas
RZ/V2N (R9A09G056) SoC. The RIIC IP is identical to that on RZ/V2H(P),
so `renesas,riic-r9a09g057` will be used as a fallback compatible,
enabling reuse of the existing driver without changes.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20250501203310.140137-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Add compatible string for Sophgo SG2044 SoC I2C controller which can be
used specifically for the SG2044 SoC.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250413223507.46480-9-inochiama@gmail.com
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Each vendor have an items entry of its own compatible, It is needless
and some can be merged as it share the same base "snps,designware-i2c"
compatible.
Merge the duplicate compatible entry into one item entry.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250413223507.46480-2-inochiama@gmail.com
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Add support for the MediaTek Dimensity 1200 (MT6893) SoC; this
chip's multiple I2C controller instances are fully compatible
with the ones found in the MT8192 SoC.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250416120303.148017-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
So far, no differences are known, so it can fallback to the default
compatible.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Add mux controller support for when the I2C lines are muxed after
signals come out of SoC and before they go to any client.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250318103622.29979-2-j-choudhary@ti.com
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Add compatible string "fsl,imx94-lpi2c" for the i.MX94 chip, which is
backward compatible with i.MX7ULP. Set it to fall back to
"fsl,imx7ulp-lpi2c".
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20250306155815.110514-1-Frank.Li@nxp.com
When the I2C QUP controller is used together with a DMA engine it needs
to vote for the interconnect path to the DRAM. Otherwise it may be
unable to access the memory quickly enough.
Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20231128-i2c-qup-dvfs-v1-2-59a0e3039111@kernkonzept.com
Similar to qcom,geni-i2c, for i2c-qup we need to vote for performance
states on the VDDCX power domain to ensure that required clock rates
can be generated correctly.
I2C is typically used with a fixed clock rate, so a single required-opp
is sufficient without a full OPP table (unlike spi-qup for example).
Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20231128-i2c-qup-dvfs-v1-1-59a0e3039111@kernkonzept.com
Add samsung,exynos8895-hsi2c dedicated compatible for representing
I2C of Exynos8895 SoC. Since there are I2C buses that aren't implemented
as a part of USIv1 blocks, they only require a single clock.
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20241228111509.896502-2-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Document support for the I2C Bus Interface (RIIC) found in the Renesas
RZ/G3E (R9A09G047) SoC. This IP is compatible with Renesas RZ/V2H
(R9A09G057) RIIC IP.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20241216202436.185773-1-biju.das.jz@bp.renesas.com
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Since there are no registers controlling the hardware parameters
IC_CAP_LOADING and IC_CLK_FREQ_OPTIMIZATION, their values can only be
declared in the device tree.
snps,bus-capacitance-pf indicates the bus capacitance in picofarads (pF).
It affects the high and low pulse width of SCL line in high speed mode.
The legal values for this property are 100 and 400 only, and default
value is 100. This property corresponds to IC_CAP_LOADING.
snps,clk-freq-optimized indicates whether the hardware reduce its
internal clock frequency by reducing the internal latency required to
generate the high period and low period of SCL line. This property
corresponds to IC_CLK_FREQ_OPTIMIZATION.
The driver can calculate the high period count and low period count of
SCL line for high speed mode based on these two properties.
Signed-off-by: Michael Wu <michael.wu@kneron.us>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Hardware is not limited to 400kHz, its documentation does mention how to
configure it for high-speed (a specific Speed-Mode enum value and
a different bus rate clock divider register to be used).
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
After EyeQ5, it is time for Mobileye EyeQ6H to reuse the Nomadik I2C
controller. Add a specific compatible because its HW integration is
slightly different from EyeQ5.
Do NOT add an example as it looks like EyeQ5 from a DT standpoint
(without the mobileye,olb property).
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
The I2C controller IP used in the Allwinner A523/T527 SoCs is
compatible with the ones used in the other recent Allwinner SoCs.
Add the A523 specific compatible string to the list of existing names
falling back to the allwinner,sun8i-v536-i2c string.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Add dt-schema for the I2C controller on the RTL9300 Ethernet switch
with integrated SoC.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
S32G2 and S32G3 SoCs use the same I2C controller as i.MX.
But there are small differences such as specific
<clock divider, register value> pairs.
So add new compatible strings 'nxp,s32g2-i2c'and 'nxp,s32g3-i2c'
for S32G2/S32G3 Socs.
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
The CCI on the Snapdragon 670 is the interface for controlling camera
hardware over I2C. Add the compatible so it can be added to the SDM670
device tree.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Theobroma Systems Mule is an MCU that emulates a set of I2C devices,
among which devices that are reachable through an I2C-mux. The devices
on the mux can be selected by writing the appropriate device number to
an I2C config register.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Farouk Bouabid <farouk.bouabid@cherry.de>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Just like RK356x and RK3588, RK3576 is compatible to the existing
rk3399 binding.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Andi Shyti <andi.shyti@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
'multi-master' property is defined by core i2c-controller schema in
dtschema package, so binding which references it and has
unevaluatedProperties:false, does not need to mention it. It is
completely redundant here.
Suggested-by: Andi Shyti <andi.shyti@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Top level defines clocks as variable from 3 to 6 items, so each clause
in if:then: should narrow it further with explicit min and maxItems.
Without minItems, the constrain from top-level is being applied, thus
qcom,msm8996-cci allows between 3 and 4 clocks.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Properties are expected to be defined in top-level "properties:" block
and further customized in "if:then:". Only one variant has power
domains, so add respective top-level property and disallow it for other
devices.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Both xxx and xxx-names properties with variable number of items should
be constrained in each "if:then:". Add missing constraints for clocks,
since we have such for clock-names.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
"if:then:" block for Tegra114 and Tegra120 I2C controllers has the same
"then" part (same clocks), so combine them.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible with
the version available on Renesas RZ/V2H (R9A09G075).
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
I2C MUXes described by the i2c-gpio-mux sometimes need a significant
amount of time to switch from a bus to another. When a new bus is
selected, the first I2C transfer can fail if it occurs too early. There
is no way to describe this transition delay that has to be waited before
starting the first I2C transfer.
Add a 'settle-time-us' property that indicates the delay to be
respected before doing the first i2c transfer.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Andi Shyti <andi.shyti@kernel.org>
Acked-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Add sm8650 compatible consistent with CAMSS CCI interfaces.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Add sm8550 compatible consistent with CAMSS CCI interfaces, the list of
clocks is reduced by removing "slow_ahb_src" clock, which is derived
from "cpas_ahb" clock.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
regarding unneeded 'driver_data' and more sanity checks in the char
device.
For the host drivers, this release includes significant updates, with
the primary change being the renaming from "master/slave" to
"controller/target" to adhere to I2C v7 and SMBus 3.2 standards.
New Support:
- Added support for Intel Arrow Lake-H.
- Added I2C support in the Arioha SoC by linking the Mediatek
I2C controller.
Cleanups:
- Added the MODULE_DESCRIPTION() macro, resolving a modpost
warning in the ALi 1563 Southbridge driver.
- Constified the regmap_config declaration in the i2c-designware
driver.
- Improved the coding style in the Renesas R-Car driver by
removing unnecessary semicolons after brackets.
General improvements:
- In the OMAP device, replaced NOIRQ_SYSTEM_SLEEP_PM_OPS with
RUNTIME_PM_OPS to enable waking up the controller during
suspend() before suspend_noirq() kicks in.
- Improved logging in the Xilinx driver.
- Added a warning (WARN()) in the Renesas R-Car driver for
spurious interrupts.
DTS Changes:
- Removed address-cell and size-cell from the Atmel at91sam,
nVidia Tegra 20, and Samsung S3c2410 devices.
- Fixed Texas Instruments OMAP4 I2C controller to comply with
the i2c-controller.yaml schema.
- Improved indentation in DTS examples for several I2C devices.
- Converted the NXP LPC1788 binding to the dt-schema.
- Added documentation for the compatible string
thead,th1520-i2c.
- Added the "power-domains" property for the Meson I2C driver.
AT24 EEPROM driver changes:
- add support for two new Microchip models
- document even more new models in DT bindings (those use fallback
compatibles so no code changes)
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEOZGx6rniZ1Gk92RdFA3kzBSgKbYFAmaagXUACgkQFA3kzBSg
KbYbXg/+Kox1Qg5LDsW9IM0YVKMbeGVCxwzNKIoL55TwW2kUOml2JZsrcTE0Ap9J
SvcpcGs6kzoU8PMzQlmmPYgIU+5NZbd50CohM1TvHE7VPcduB+ydHfo61aF48obU
K3biAxALkcNYG4ab5i83D04Fcfwwgmt5wU/nXvcySTRteeBOtcB+MniZ0fJWG4q1
3czYndwLgWwKa+xOaI0Y1tf5Fc8LEtyGCDQuvDtbA0/cr4RjAYVo9t8cPsKi0Ywk
WEsgk7e2u74UwepmR/SQcKJ25Z70hf9k0vsyGVCPqqGNZPeCOWhiFgphU57Dm2Gm
IX5CncwMT/5jYa1AoZmWmc2SkDIkk+RXq6zaOgncuDtFy78A+DHSzRSnOk5cjXX+
cNu5Er5UEzVxnJGM46C+1/60LnqIpQYyEW5goPhr91So8UPMC+PaK2eNJ+nknSxS
jc2832KlWcKj0Hun7X6fbVHNGX/AKpNzwrYjOy7Rxd0G/ViaspzKSD+eukAFQuKX
PX5pGcO/syzGIzXMP7aRoQ+I0TIIpTaIB9UeuCTzTSzYYmtI/yKgDp9Cbi5yPGD8
EXEVPfL3jmjxMmoYUXVPeE7qHMLm/wlrhrMvhhBKHsvzQ3MfSw9J/lcEnuKGiWYu
PEKRsIdlp2qJL0tseoB/dlwWIMgW7XHT5pg4I9FoX1H1UWC89cs=
=perV
-----END PGP SIGNATURE-----
Merge tag 'i2c-for-6.11-rc1-try2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c fixes from Wolfram Sang:
"The I2C core gains documentation updates for the testunit, a cleanup
regarding unneeded 'driver_data' and more sanity checks in the char
device.
For the host drivers, this release includes significant updates, with
the primary change being the renaming from "master/slave" to
"controller/target" to adhere to I2C v7 and SMBus 3.2 standards.
New Support:
- Added support for Intel Arrow Lake-H
- Added I2C support in the Arioha SoC by linking the Mediatek I2C
controller
Cleanups:
- Added the MODULE_DESCRIPTION() macro, resolving a modpost warning
in the ALi 1563 Southbridge driver.
- Constified the regmap_config declaration in the i2c-designware
driver.
- Improved the coding style in the Renesas R-Car driver by removing
unnecessary semicolons after brackets.
General improvements:
- In the OMAP device, replaced NOIRQ_SYSTEM_SLEEP_PM_OPS with
RUNTIME_PM_OPS to enable waking up the controller during suspend()
before suspend_noirq() kicks in.
- Improved logging in the Xilinx driver.
- Added a warning (WARN()) in the Renesas R-Car driver for spurious
interrupts.
DTS Changes:
- Removed address-cell and size-cell from the Atmel at91sam, nVidia
Tegra 20, and Samsung S3c2410 devices.
- Fixed Texas Instruments OMAP4 I2C controller to comply with the
i2c-controller.yaml schema.
- Improved indentation in DTS examples for several I2C devices.
- Converted the NXP LPC1788 binding to the dt-schema.
- Added documentation for the compatible string thead,th1520-i2c.
- Added the "power-domains" property for the Meson I2C driver.
AT24 EEPROM driver changes:
- add support for two new Microchip models
- document even more new models in DT bindings (those use fallback
compatibles so no code changes)"
* tag 'i2c-for-6.11-rc1-try2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (87 commits)
i2c: document new callbacks in i2c_algorithm
dt-bindings: i2c: amlogic,meson6-i2c: add optional power-domains
dt-bindings: i2c: at91: Add sama7d65 compatible string
i2c: st: reword according to newest specification
i2c: cpm: reword according to newest specification
i2c: virtio: reword according to newest specification
i2c: nvidia-gpu: reword according to newest specification
i2c: viai2c: reword according to newest specification
i2c: viperboard: reword according to newest specification
i2c: uniphier: reword according to newest specification
i2c: uniphier-f: reword according to newest specification
i2c: tiny-usb: reword according to newest specification
i2c: thunderx-pcidrv: reword according to newest specification
i2c: tegra-bpmp: reword according to newest specification
i2c: taos-evm: reword according to newest specification
i2c: sun6i-p2wi: reword according to newest specification
i2c: stm32f4: reword according to newest specification
i2c: sprd: reword according to newest specification
i2c: sis5595: reword according to newest specification
i2c: rzv2m: reword according to newest specification
...
DT Bindings:
- Convert and add a bunch of IBM FSI related bindings
- Add a new schema listing legacy compatibles which will (probably)
never be documented. This will silence various checks warning about
them.
- Add bindings for Sierra Wireless mangOH Green SPI IoT interface, new
Arm 2024 Cortex and Neoverse CPUs, QCom sc8180x PDC, QCom SDX75 GPI
DMA, imx8mp/imx8qxp fsl,irqsteer, and Renesas RZ/G2UL CRU and CSI-2
blocks
- Convert Spreadtrum sprd-timer, FSL cpm_qe, FSL fsl,ls-scfg-msi, FSL
q(b)man-*, FSL qoriq-mc, and img,pdc-wdt bindings to DT schema
- Drop obsolete stericsson,abx500.txt
DT core:
- Update dtc to upstream version v1.7.0-93-g1df7b047fe43
- Add support to run DT validation on DTs with applied overlays
- Add helper for creating boolean properties in dynamic nodes and use
that for dynamic PCI nodes
- Clean-up early parsing of '#{address,size}-cells'
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAmaW6UAACgkQ+vtdtY28
YcOyHRAAoDbhRxRtsF7pWwbiaEFi4y7yTyX6ogxGM3gL5xoXmT7Xri0OWakbHcTp
gfy9mWdeI9lw4eEheGDiX7qI66ax8SuuQjZ96wxMvsflFhnaLsL+088G208uGCMU
BuJroP2hvgOixeNi4hyy9ia2j036VpLLTqLHHFK7kzC7NCX2cWpaV2Tk7knHV8OY
OrJIUeRhcaTmotBJB0A2G+AkHTXQkfR1FdULvIQP8dewA2RI7R2Y6jffmh53gK+f
hLo1geUBVWe8y8xNjz9LVDYxrKPawAPOwO/n92kaSdw780suRUs4oq4L2+o1rYzV
sXTfx3+pZuL80FfTPheT4mHTTMZ2Hhq2wa4u2CWK4SHwv9KFBefYp6w7nlMELkM/
BQ1YLjtPh/GhywDa1TxGWPOha3wPFCewBNJuo4MrHKjhvSKBn7OPCdyNPBAahwQa
jFypbcWFhtcXtNTa4M9LhGJLlNK4RpTp4RGRcYvTNtZSa0TTUVz+1jvQ4ToPnXIf
C5VV1c370NpRJ1BUGeY8R4k946hzJAOxgaMGlkLaW90Cwn16VTCy666R9hwI1nx5
vdftlbgTHbZ/KOe6zTM6ywOsol8na1Wk7rqyfKR2vWHnmtj/DvFrKwXvBiKR0SuN
ru7vdOdi13YxcOmkgPoso+kBf1V0qELzxyrC4I8gPiOm68bPLZg=
=tjMz
-----END PGP SIGNATURE-----
Merge tag 'devicetree-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT Bindings:
- Convert and add a bunch of IBM FSI related bindings
- Add a new schema listing legacy compatibles which will (probably)
never be documented. This will silence various checks warning about
them.
- Add bindings for Sierra Wireless mangOH Green SPI IoT interface,
new Arm 2024 Cortex and Neoverse CPUs, QCom sc8180x PDC, QCom SDX75
GPI DMA, imx8mp/imx8qxp fsl,irqsteer, and Renesas RZ/G2UL CRU and
CSI-2 blocks
- Convert Spreadtrum sprd-timer, FSL cpm_qe, FSL fsl,ls-scfg-msi, FSL
q(b)man-*, FSL qoriq-mc, and img,pdc-wdt bindings to DT schema
- Drop obsolete stericsson,abx500.txt
DT core:
- Update dtc to upstream version v1.7.0-93-g1df7b047fe43
- Add support to run DT validation on DTs with applied overlays
- Add helper for creating boolean properties in dynamic nodes and use
that for dynamic PCI nodes
- Clean-up early parsing of '#{address,size}-cells'"
* tag 'devicetree-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (39 commits)
dt-bindings: timer: sprd-timer: convert to YAML
dt-bindings: incomplete-devices: document devices without bindings
dt-bindings: trivial-devices: document the Sierra Wireless mangOH Green SPI IoT interface
scripts/dtc: Update to upstream version v1.7.0-93-g1df7b047fe43
dt-bindings: soc: fsl: Add fsl,ls1028a-reset for reset syscon node
dt-bindings: soc: fsl: cpm_qe: convert to yaml format
dt-bindings: i2c: i2c-fsi: Convert to json-schema
dt-bindings: fsi: Document the FSI Hub Controller
dt-bindings: fsi: Document the AST2700 FSI controller
dt-bindings: fsi: ast2600-fsi-master: Convert to json-schema
dt-bindings: fsi: ibm,i2cr-fsi-master: Reference common FSI controller
dt-bindings: fsi: Document the FSI controller common properties
dt-bindings: fsi: Document the IBM SBEFIFO engine
dt-bindings: fsi: p9-occ: Convert to json-schema
dt-bindings: fsi: Document the IBM SCOM engine
dt-bindings: fsi: fsi2spi: Document SPI controller child nodes
dt-bindings: interrupt-controller: convert fsl,ls-scfg-msi to yaml
dt-bindings: soc: fsl: Convert q(b)man-* to yaml format
dt-bindings: misc: fsl,qoriq-mc: convert to yaml format
dt-bindings: drop stale Anson Huang from maintainers
...
On newer SoCs, the I2C hardware can require a power domain to operate.
Since the same compatible is used for older and newer SoCs make
power-domains property optional.
Signed-off-by: George Stark <gnstark@salutedevices.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Add compatible string for sama7d65. Like sama7g5, it currently binds to
"microchip,sam9x60-i2c" compatible string for this driver.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
