mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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loongarch-next
178 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Linus Torvalds
|
0f46f50845 |
soc: driver updates for 6.17
Changes are all over the place, but very little sticks out as noteworthy. There is a new misc driver for the Raspberry Pi 5's RP1 multifunction I/O chip, along with hooking it up to the pinctrl and clk frameworks. The reset controller and memory subsystems have mainly small updates, but there are two new reset drivers for the K230 and VC1800B SoCs, and new memory driver support for Tegra264. The ARM SMCCC and SCMI firmware drivers gain a few more features that should help them be supported across more environments. Similarly, the SoC specific firmware on Tegra and Qualcomm get minor enhancements and chip support. In the drivers/soc/ directory, the ASPEED LPC snoop driver gets an overhaul for code robustness, the Tegra and Qualcomm and NXP drivers grow to support more chips, while the Hisilicon, Mediatek and Renesas drivers see mostly janitorial fixes. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmiEmIcACgkQmmx57+YA GNkE4g/6A2OKti+qtIsLt10zS7paGP38ftu9ad27WC54AOGgVk4ZXt8mVGRmqOf+ BICIM+wc4gehdvRJTRnq3gZg3e1puuYdcMuBOh4qsghRMjdYUKfNairtn/iX7d+f e5auzz5/gV7MWNM7jiQNydCqZSeV6u2/cqD5iRCrRgaB5FOG4yY1BkAsah1UzZjk MycudqjkK4IX5zp5oqXB/PoesULAbB2unjvfw194LATYSqmcRLQRWFdv4aM0R6ba TDP5x0d95nhMTNWif3495zc2WxdSYzbD4lNv44RPpKDywqBj+qFBI/EpMFkxQ5Hy cqv60Dm+/tx+DBO/Ma0zJzsV4ChRIEBNkTUh36OxmYxq70x1T4FEynZ6IT8a8dXD ltjHwOcTHp1M0OpNj+PIFBD+ohWFWKOo+T9GRtTInLjUGBlJA6LK9i4Lb0DaIyRt DmmvbZCwh0PI/nZiyQzw7rsXWwqDcqeF8FScw+9ooBk7Z7Jr1gMc52ya0qrRWQ8w Tr3D+lNE0aDfErnx4RrNsjD8lpX4nOfRFvuWSTlWqkBjGhoDP/tnNi2RCWmbXo2Z PDDWLnECo6o1aIxYO/tHjbFKVJB38p4e/LLP89htu8dFxSZKnVzxosnOvEVWS8+Y a0oZb9j1tAOYHmMWDm+zaQ7BlK9CMURNTdUcnqNqIvZpHnHz9M8= =7T40 -----END PGP SIGNATURE----- Merge tag 'soc-drivers-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "Changes are all over the place, but very little sticks out as noteworthy. There is a new misc driver for the Raspberry Pi 5's RP1 multifunction I/O chip, along with hooking it up to the pinctrl and clk frameworks. The reset controller and memory subsystems have mainly small updates, but there are two new reset drivers for the K230 and VC1800B SoCs, and new memory driver support for Tegra264. The ARM SMCCC and SCMI firmware drivers gain a few more features that should help them be supported across more environments. Similarly, the SoC specific firmware on Tegra and Qualcomm get minor enhancements and chip support. In the drivers/soc/ directory, the ASPEED LPC snoop driver gets an overhaul for code robustness, the Tegra and Qualcomm and NXP drivers grow to support more chips, while the Hisilicon, Mediatek and Renesas drivers see mostly janitorial fixes" * tag 'soc-drivers-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (100 commits) bus: del unnecessary init var soc: fsl: qe: convert set_multiple() to returning an integer pinctrl: rp1: use new GPIO line value setter callbacks soc: hisilicon: kunpeng_hccs: Fix incorrect log information dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatible dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side channel dt-bindings: firmware: qcom,scm: document Milos SCM Firmware Interface soc: qcom: socinfo: Add support to retrieve APPSBL build details soc: qcom: pmic_glink: fix OF node leak soc: qcom: spmi-pmic: add more PMIC SUBTYPE IDs soc: qcom: socinfo: Add PM7550 & PMIV0108 PMICs soc: qcom: socinfo: Add SoC IDs for SM7635 family dt-bindings: arm: qcom,ids: Add SoC IDs for SM7635 family firmware: qcom: scm: request the waitqueue irq *after* initializing SCM firmware: qcom: scm: initialize tzmem before marking SCM as available firmware: qcom: scm: take struct device as argument in SHM bridge enable firmware: qcom: scm: remove unused arguments from SHM bridge routines soc: qcom: rpmh-rsc: Add RSC version 4 support memory: tegra: Add Tegra264 MC and EMC support firmware: tegra: bpmp: Fix build failure for tegra264-only config ... |
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Linus Torvalds
|
115e74a29b |
soc: dt changes for 6.17
There are a few new variants of existing chips:
- mt6572 is an older mobile phone chip from mediatek that was
extremely popular a decade ago but never got upstreamed until now.
- exynos2200 is a recent high-end mobile phone chip used in a
few Samsung phones like the Galaxy S22
- Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
(R8A779H0) and used in automotive applications
- Tegra264 is a new chip from NVIDIA, but support is fairly minimal
for now, and not much information is public about it.
There are five more chips in a separate branch, as those are new
chip families that I merged along with the necessary infrastructure.
New board support is not that exciting, with a total of 33 newly
added machines here:
- Evaluation platforms for the chips above, plus TI am62d2 and
Sophgo sg2042.
- Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
imx95.
- Two newly added ASPEED BMC based motherboards, and one that got
removed
- Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
msm8976 SoCs
- Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1
- A set-top box based on Amlogic meson-gxm.
Updates for existing machines are spread over all the above families.
One notable change here is support for the RP1 I/O chip used in
Raspberry Pi 5.
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Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There are a few new variants of existing chips:
- mt6572 is an older mobile phone chip from mediatek that was
extremely popular a decade ago but never got upstreamed until now
- exynos2200 is a recent high-end mobile phone chip used in a few
Samsung phones like the Galaxy S22
- Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
(R8A779H0) and used in automotive applications
- Tegra264 is a new chip from NVIDIA, but support is fairly minimal
for now, and not much information is public about it
There are five more chips in a separate branch, as those are new chip
families that I merged along with the necessary infrastructure.
New board support is not that exciting, with a total of 33 newly added
machines here:
- Evaluation platforms for the chips above, plus TI am62d2 and Sophgo
sg2042
- Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
imx95
- Two newly added ASPEED BMC based motherboards, and one that got
removed
- Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
msm8976 SoCs
- Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1
- A set-top box based on Amlogic meson-gxm
Updates for existing machines are spread over all the above families.
One notable change here is support for the RP1 I/O chip used in
Raspberry Pi 5"
* tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits)
riscv: dts: sophgo: fix mdio node name for CV180X
riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
riscv: dts: sophgo: add ethernet GMAC device for sg2042
riscv: dts: sophgo: Enable ethernet device for Huashan Pi
riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
riscv: dts: sophgo: Add ethernet device for cv18xx
riscv: dts: sophgo: sg2044: add pmu configuration
riscv: dts: sophgo: sg2044: add ziccrse extension
riscv: dts: sophgo: add zfh for sg2042
riscv: dts: sophgo: add ziccrse for sg2042
riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
riscv: dts: sophgo: sg2044: add MSI device support for SG2044
riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
...
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Krzysztof Kozlowski
|
0121898ec0 |
dt-bindings: Correct indentation and style in DTS example
DTS example in the bindings should be indented with 2- or 4-spaces and aligned with opening '- |', so correct any differences like 3-spaces or mixtures 2- and 4-spaces in one binding. No functional changes here, but saves some comments during reviews of new patches built on existing code. Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # For MMC Acked-by: Lee Jones <lee@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Link: https://lore.kernel.org/r/20250107131456.247610-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250725100241.120106-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
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Arnd Bergmann
|
1037b300df |
Allwinner device tree changes for 6.17
This branch includes a change shared with the clk tree for adding the missing PPU0 reset on the A523. The PM domain DT binding immutable branch is also included, which brings in v6.16-rc2, as well as PM domain bindings for other platforms. Other changes include: - RGB666 LCD pin definitions for the V3s PE pins and V3 PD pins - node order fixes for the A523 dtsi - UART1 pin definitions for A523 - Allwinner board DT binding cleanup - EMAC support on A100/A133 - Enabled on the Liontron H-A133L board - SID efuse, power controllers and GPU added for A523 - A523 GPU enabled on all existing boards New boards: - Xunlong OrangePi 4A with the Allwinner T527 SoC. -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAmh2jp0OHHdlbnNAY3Np ZS5vcmcACgkQOJpUIZwPJDBDIQ/8C/vnF+mjoNj/Gci0AUMbtVVvI4G28x8bsGVP jy3Z2dBuEQvU4eGvOKGyM9oJ5WfQBlpRS9nlRf/NHu/tASc7gXGHb7OJOlAocIUr ny3MpO2un0nx6HbtR6RtciSSLoasB6HtAKBscxmapJ3TiZBbjDtI7Z5l+Vxx75z8 Fo6xxQ9n+Iyxo3X6wZi9vp/d15Xz4LVy2iarN/JY+jywGtKZOcpsqEKqIV7m6Lcf 6pL2/ZaX38JzOdCY4lNsHUA827Ep/0waXirmUg0rvi8BpI4s1Cysh6XIbyrlQjaK xbqRvWWg0ZEaC3j2rcUTLaXREMsl5OFkX/5ywCysh0K76kKwxDvnPnDYUq3yOlwL qBO7PUEdCywqfSaaNFR+d8JqnALFT/h5P1KJhx7L2PpNpl3vH/TFy2EIVZgy+A2W p2+hkmqB211uJpzWdQ98ED0aIRErDM1vq0pi3KLqFGATmgp/ZQ53UbtrWDwI1NEN TUJK80ZztmyqGWlMTsSIHajgt7OAPI+Gc/gIv8fFLbciHoYV68HBAO3t6ljDKbOe grwLFhPLe3OELGkKsoOsrSsDJ39ijYpXMw4ssuDQY+TDdEtCrMC1F/NPdS05NQx1 igjLrUHOD6dMo4azw4uOPNosXir9+Rjywuqeuj/CBJfJkCqWDCh9OJFhWkaFMi01 ATqMzjY= =CwjI -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmh/7HUACgkQmmx57+YA GNkiWA//XXWjj5W1dEf8xWJFwL5YwJVkX0s+5XPWnAJ8YtLuuttt64bO/dCr74SL P6HeEsLLgW7+/LCCd0owkCz+GW+xGTQ5h/NfWgI6tAH73LV4DZ3XGztts06gUuZ1 DXzWJpRiV3CBUgN52eXdxvjsM4wgDwShck5DH21SbhQf3NpCB7YAtXi3eelqgHrh zrsR4UzfF2b/efKMeJP6vORLT4KkumS+IJsMS6cMErIXFeu/kOY7q5f8jvF6FftL 117kyEl55OiFV5E0S15zdnSGxiNPYWnwi00BUd2HDfxAer0/ow0lbW0bUwlAUd4V a7mTxi74Wv8QBgIw/tn+o5Fi24wz86c+Lks85rRC6YlkuQrExaNK2bC7Vzxc7imS PakQQnQMnIWA7kf/log2PdIX89gNYe7Lh5x7SKjvd0UmIvsgbwMX51e18P52it0a /81ntWhwhYoE7A+qVKZYleb2dG12/893hdW1lxKGnjiBsEkL15U9fsIKFAzgjKCb UHrr/dcPEcCedytSnTkOqiws1bscv9zHbc7qN0VEPtSbRwsVUHyDRcw3XFcWRSgK JlfiCuYvr+aOKegKihXauxLGDXwK1Q1GK61hMcwJGRocswENT2LA/vcIYDR0e8hR CYkc0IilHKyf/14HF+qBj5roPZkufJYS9T0xLs1tEsKRxMbeomI= =v3GV -----END PGP SIGNATURE----- Merge tag 'sunxi-dt-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt Allwinner device tree changes for 6.17 This branch includes a change shared with the clk tree for adding the missing PPU0 reset on the A523. The PM domain DT binding immutable branch is also included, which brings in v6.16-rc2, as well as PM domain bindings for other platforms. Other changes include: - RGB666 LCD pin definitions for the V3s PE pins and V3 PD pins - node order fixes for the A523 dtsi - UART1 pin definitions for A523 - Allwinner board DT binding cleanup - EMAC support on A100/A133 - Enabled on the Liontron H-A133L board - SID efuse, power controllers and GPU added for A523 - A523 GPU enabled on all existing boards New boards: - Xunlong OrangePi 4A with the Allwinner T527 SoC. * tag 'sunxi-dt-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits) arm64: dts: allwinner: a523: enable Mali GPU for all boards arm64: dts: allwinner: a523: add Mali GPU node arm64: dts: allwinner: a523: Add power controller device nodes dt-bindings: power: Add A523 PPU and PCK600 power controllers arm64: dts: allwinner: A523: Add SID controller node arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support arm64: dts: allwinner: a100: Add EMAC support arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII dt-bindings: arm: sunxi: Combine board variants into enums dt-bindings: power: qcom,rpmpd: document the Milos RPMh Power Domains arm64: dts: allwinner: t527: Add OrangePi 4A board arm64: dts: allwinner: a523: Add UART1 pins arm64: dts: allwinner: a523: Move rgmii0 pins to correct location arm64: dts: allwinner: a523: Move mmc nodes to correct position dt-bindings: arm: sunxi: Add Xunlong OrangePi 4A board ARM: dts: sun8i: v3: Add RGB666 LCD PD pins definition ARM: dts: sun8i: v3s: Add RGB666 LCD PE pins definition dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset dt-bindings: firmware: thead,th1520: Add resets for GPU clkgen dt-bindings: rockchip: pmu: Add compatible for RK3528 ... Link: https://lore.kernel.org/r/aHaQFe3Lr8Qzyb1M@wens.tw Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Luca Weiss
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4405f3f7b4 |
dt-bindings: firmware: qcom,scm: document Milos SCM Firmware Interface
Document the SCM Firmware Interface on the Milos SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250713-sm7635-fp6-initial-v2-4-e8f9a789505b@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Thierry Reding
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52f117f8a7 |
dt-bindings: firmware: Document Tegra264 BPMP
While the BPMP found on Tegra264 is similar to the versions found on previous chips and should be backwards-compatible, some changes could eventually be needed. Anticipate such changes and introduce a chip- specific compatible string. Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250506133118.1011777-5-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com> |
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Michal Wilczynski
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7226b28ac7 |
dt-bindings: firmware: thead,th1520: Add resets for GPU clkgen
Extend the TH1520 AON to describe the GPU clkgen reset line, required for proper GPU clock and reset sequencing. The T-HEAD TH1520 GPU requires coordinated management of two clocks (core and sys) and two resets (GPU core reset and GPU clkgen reset). Only the clkgen reset is exposed at the AON level, to support SoC specific initialization handled through a dedicated auxiliary power sequencing driver. The GPU core reset remains described in the GPU device node, as from the GPU driver's perspective, there is only a single reset line [1]. This follows upstream maintainers' recommendations [2] to abstract SoC specific details into the PM domain layer rather than exposing them to drivers directly. Link: https://lore.kernel.org/all/816db99d-7088-4c1a-af03-b9a825ac09dc@imgtec.com/ - [1] Link: https://lore.kernel.org/all/38d9650fc11a674c8b689d6bab937acf@kernel.org/ - [2] Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Drew Fustini <drew@pdp7.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Link: https://lore.kernel.org/r/20250623-apr_14_for_sending-v6-2-6583ce0f6c25@samsung.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> |
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Linus Torvalds
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ec71f661a5 |
soc: devicetree updates for 6.16
There are 11 newly supported SoCs, but these are all either new
variants of existing designs, or straig reuses of the existing
chip in a new package:
- RK3562 is a new chip based on the old Cortex-A53 core, apparently
a low-cost version of the Cortex-A55 based RK3568/RK3566.
- NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different
set of on-chip peripherals.
- Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2 family
- Amlogic S6/S7/S7D
- Samsung Exynos7870 is an older chip similar to Exynos7885
- WonderMedia wm8950 is a minor variation on the wm8850 chip
- Amlogic s805y is almost idential to s805x
- Allwinner A523 is similar to A527 and T527
- Qualcomm MSM8926 is a variant of MSM8226
- Qualcomm Snapdragon X1P42100 is related to R1E80100
There are also 65 boards, including reference designs for the chips
above, this includes
- 12 new boards based on TI K3 series chips, most of them from
Toradex
- 10 devices using Rockchips RK35xx and PX30 chips
- 2 phones and 2 laptops based on Qualcomm Snapdragon designs
- 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses
- 3 Samsung Galaxy phones based on Exynos7870
- 5 Allwinner based boards using a variety of ARMv8 chips
- 9 32-bit machines, each based on a different SoC family
Aside from the new hardware, there is the usual set of cleanups and
newly added hardware support on existing machines, for a total of 965
devicetree changesets.
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Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There are 11 newly supported SoCs, but these are all either new
variants of existing designs, or straight reuses of the existing chip
in a new package:
- RK3562 is a new chip based on the old Cortex-A53 core, apparently a
low-cost version of the Cortex-A55 based RK3568/RK3566.
- NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different
set of on-chip peripherals.
- Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2
family
- Amlogic S6/S7/S7D
- Samsung Exynos7870 is an older chip similar to Exynos7885
- WonderMedia wm8950 is a minor variation on the wm8850 chip
- Amlogic s805y is almost idential to s805x
- Allwinner A523 is similar to A527 and T527
- Qualcomm MSM8926 is a variant of MSM8226
- Qualcomm Snapdragon X1P42100 is related to R1E80100
There are also 65 boards, including reference designs for the chips
above, this includes
- 12 new boards based on TI K3 series chips, most of them from
Toradex
- 10 devices using Rockchips RK35xx and PX30 chips
- 2 phones and 2 laptops based on Qualcomm Snapdragon designs
- 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses
- 3 Samsung Galaxy phones based on Exynos7870
- 5 Allwinner based boards using a variety of ARMv8 chips
- 9 32-bit machines, each based on a different SoC family
Aside from the new hardware, there is the usual set of cleanups and
newly added hardware support on existing machines, for a total of 965
devicetree changesets"
* tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits)
MAINTAINERS, mailmap: update Sven Peter's email address
arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency
arm64: dts: nuvoton: Add pinctrl
ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings
arm64: dts: blaize-blzp1600: Enable GPIO support
dt-bindings: clock: socfpga: convert to yaml
arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node
arm64: dts: rockchip: fix rk3562 pcie unit addresses
arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node
arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi
arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node
arm64: dts: rockchip: fix rk3576 pcie unit addresses
arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588
arm64: dts: rockchip: Add missing SFC power-domains to rk3576
Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0"
arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes
arm64: dts: mt6359: Rename RTC node to match binding expectations
arm64: dts: mt8365-evk: Add goodix touchscreen support
arm64: dts: mediatek: mt8188: Add missing #reset-cells property
arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board
...
|
||
|
Arnd Bergmann
|
4e61c011b0 |
Arm SCMI updates for v6.16
1. Quirk framework to handle buggy firmware
With SCMI gaining broader adoption across arm64 platforms, it's
increasingly important to address how we consistently manage out-of-spec
SCMI firmware already deployed in the field. This change introduces a
lightweight quirk framework built around static_keys, enabling developers to:
- Define quirks and their match criteria, which can include:
o A list of compatibles ({ comp, comp2, NULL })
o Vendor ID / Sub-Vendor ID
o Firmware implementation version ranges ([Min_Vers, Max_Vers])
Matching proceeds from the most specific (longest match) to the least
specific. NULL entries are treated as wildcards (i.e., match any value).
This flexibility allows matching very specific combinations or just a
general compatible string.
The quirk code blocks/snippets implementing the workaround are placed near
their intended usage and guarded by a static_key that's tied to the quirk.
Once the SCMI core stack is initialized and retrieves platform info via the
base protocol, any matching quirks will have their associated static_keys
enabled.
2. Quirk for Qualcomm X1E platforms
On some Qualcomm X1E platforms, such as the Lenovo ThinkPad T14s, the
SCMI firmware fails to set the FastChannel support bit for PERF_LEVEL_GET,
yet it crashes when the driver attempts to fall back to standard messaging
which is clearly out-of-spec behavior.
To work around this, the new SCMI quirk framework is used to
unconditionally enable FC initialization for this firmware version.
In the future, once the fixed firmware version is identified, an upper
version bound can be added to the quirk match criteria. Alternatively,
matching can be further restricted using a SoC-specific compatible string
if always enabling FC proves problematic elsewhere.
3. Support for NXP i.MX LMM/CPU vendor protocol extensions
The i.MX95 System Manager (SM) implements Logical Machine Management (LMM)
and a CPU protocol to manage Logical Machines (LM) and CPUs (e.g., M7).
These changes integrate the vendor-specific protocol extensions
implementing the LMM and CPU protocols for the i.MX95, facilitating
standardized communication between the operating system and the platform's
firmware, which will be used by remoteproc drivers. The changes also
include the necessary device tree bindings.
4. Miscellaneous cleanups/changes
These mainly include polling support in SCMI raw mode. The cleanups
centralize error logging for SCMI device creation into a single helper
function, consolidate the device matching logic into a single function, and
ensure that devices must have a name for registration—removing support for
unnamed devices when matching drivers and devices for probing. Transport
devices are now excluded from bus matching, and the correct assignment of
the parent device for the arm-scmi platform device is ensured in the
transport drivers.
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Merge tag 'scmi-updates-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers
Arm SCMI updates for v6.16
1. Quirk framework to handle buggy firmware
With SCMI gaining broader adoption across arm64 platforms, it's
increasingly important to address how we consistently manage out-of-spec
SCMI firmware already deployed in the field. This change introduces a
lightweight quirk framework built around static_keys, enabling developers to:
- Define quirks and their match criteria, which can include:
o A list of compatibles ({ comp, comp2, NULL })
o Vendor ID / Sub-Vendor ID
o Firmware implementation version ranges ([Min_Vers, Max_Vers])
Matching proceeds from the most specific (longest match) to the least
specific. NULL entries are treated as wildcards (i.e., match any value).
This flexibility allows matching very specific combinations or just a
general compatible string.
The quirk code blocks/snippets implementing the workaround are placed near
their intended usage and guarded by a static_key that's tied to the quirk.
Once the SCMI core stack is initialized and retrieves platform info via the
base protocol, any matching quirks will have their associated static_keys
enabled.
2. Quirk for Qualcomm X1E platforms
On some Qualcomm X1E platforms, such as the Lenovo ThinkPad T14s, the
SCMI firmware fails to set the FastChannel support bit for PERF_LEVEL_GET,
yet it crashes when the driver attempts to fall back to standard messaging
which is clearly out-of-spec behavior.
To work around this, the new SCMI quirk framework is used to
unconditionally enable FC initialization for this firmware version.
In the future, once the fixed firmware version is identified, an upper
version bound can be added to the quirk match criteria. Alternatively,
matching can be further restricted using a SoC-specific compatible string
if always enabling FC proves problematic elsewhere.
3. Support for NXP i.MX LMM/CPU vendor protocol extensions
The i.MX95 System Manager (SM) implements Logical Machine Management (LMM)
and a CPU protocol to manage Logical Machines (LM) and CPUs (e.g., M7).
These changes integrate the vendor-specific protocol extensions
implementing the LMM and CPU protocols for the i.MX95, facilitating
standardized communication between the operating system and the platform's
firmware, which will be used by remoteproc drivers. The changes also
include the necessary device tree bindings.
4. Miscellaneous cleanups/changes
These mainly include polling support in SCMI raw mode. The cleanups
centralize error logging for SCMI device creation into a single helper
function, consolidate the device matching logic into a single function, and
ensure that devices must have a name for registration—removing support for
unnamed devices when matching drivers and devices for probing. Transport
devices are now excluded from bus matching, and the correct assignment of
the parent device for the arm-scmi platform device is ensured in the
transport drivers.
* tag 'scmi-updates-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
firmware: arm_scmi: quirk: Force perf level get fastchannel
firmware: arm_scmi: quirk: Fix CLOCK_DESCRIBE_RATES triplet
firmware: arm_scmi: Add common framework to handle firmware quirks
firmware: arm_scmi: Ensure that the message-id supports fastchannel
MAINTAINERS: add entry for i.MX SCMI extensions
firmware: imx: Add i.MX95 SCMI CPU driver
firmware: imx: Add i.MX95 SCMI LMM driver
firmware: arm_scmi: imx: Add i.MX95 CPU Protocol
firmware: arm_scmi: imx: Add i.MX95 LMM protocol
dt-bindings: firmware: Add i.MX95 SCMI LMM and CPU protocol
firmware: arm_scmi: imx: Add LMM and CPU documentation
firmware: arm_scmi: Add polling support to raw mode
firmware: arm_scmi: Exclude transport devices from bus matching
firmware: arm_scmi: Assign correct parent to arm-scmi platform device
firmware: arm_scmi: Refactor error logging from SCMI device creation to single helper
firmware: arm_scmi: Refactor device matching logic to eliminate duplication
firmware: arm_scmi: Ensure scmi_devices are always matched by name as well
Link: https://lore.kernel.org/r/20250507134713.49039-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||
|
Arnd Bergmann
|
0d57ac1f92 |
SoCFPGA DTS updates for v6.15
- Updates to dt-bindings
- Document Agilex5 NAND daughter board
- Convert Stratix10 FPGA Manager to json-schema
- Convert Stratix10 Service Layer to json-schema
- Add document for Terasic's DE10-nano board
- Add support for Agilex5 NAND daughter board
- Add basic support for Terasic's DE10-nano board
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Merge tag 'socfpga_dts_updates_for_v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA DTS updates for v6.15
- Updates to dt-bindings
- Document Agilex5 NAND daughter board
- Convert Stratix10 FPGA Manager to json-schema
- Convert Stratix10 Service Layer to json-schema
- Add document for Terasic's DE10-nano board
- Add support for Agilex5 NAND daughter board
- Add basic support for Terasic's DE10-nano board
* tag 'socfpga_dts_updates_for_v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: socfpga: agilex: Add dma channel id for spi
arm64: dts: socfpga: agilex5: add led and memory nodes
arm64: dts: intel: socfpga_agilex: add frequencies to internal oscillators
ARM: dts: socfpga: Add basic support for Terrasic's de10-nano
dt-bindings: altera: Add compatible for Terasic's DE10-nano
arm64: dts: socfpga: agilex5: add qspi flash node
dt-bindings: firmware: stratix10: Convert to json-schema
dt-bindings: fpga: stratix10: Convert to json-schema
arm64: dts: socfpga: agilex5: fix gpio0 address
arm64: dts: socfpga: agilex5: add NAND daughter board
dt-bindings: intel: document Agilex5 NAND daughter board
Link: https://lore.kernel.org/r/20250326121152.1739873-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||
|
Peng Fan
|
73b7a51b74 |
dt-bindings: firmware: Add i.MX95 SCMI LMM and CPU protocol
Add i.MX SCMI Extension protocols bindings for: - Logic Machine Management(LMM) Protocol intended for boot, shutdown, and reset of other logical machines (LM). It is usually used to allow one LM to manager another used as an offload or accelerator engine.. - CPU Protocol. allows an agent to start or stop a CPU. It is used to manage auxiliary CPUs in an LM (e.g. additional cores in an AP cluster). Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Message-Id: <20250408-imx-lmm-cpu-v4-2-4c5f4a456e49@nxp.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> |
||
|
André Draszik
|
935e5bd95d |
dt-bindings: firmware: google,gs101-acpm-ipc: add PMIC child node
The PMIC is supposed to be a child of ACPM, add it here to describe the connection. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20250409-s2mpg10-v4-3-d66d5f39b6bf@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
||
|
Linus Torvalds
|
a9fc230497 |
soc: driver updates for 6.15, part 1
These are the updates for SoC specific drivers and related subsystems:
- Firmware driver updates for SCMI, FF-A and SMCCC firmware interfaces,
adding support for additional firmware features including SoC
identification and FF-A SRI callbacks as well as various bugfixes
- Memory controller updates for Nvidia and Mediatek
- Reset controller support for microchip sam9x7 and imx8qxp/imx8qm
- New hardware support for multiple Mediatek, Renesas and Samsung Exynos chips
- Minor updates on Zynq, Qualcomm, Amlogic, TI, Samsung, Nvidia and Apple chips
There will be a follow up with a few more driver updates that are still
causing build regressions at the moment.
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Merge tag 'soc-drivers-6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"These are the updates for SoC specific drivers and related subsystems:
- Firmware driver updates for SCMI, FF-A and SMCCC firmware
interfaces, adding support for additional firmware features
including SoC identification and FF-A SRI callbacks as well as
various bugfixes
- Memory controller updates for Nvidia and Mediatek
- Reset controller support for microchip sam9x7 and imx8qxp/imx8qm
- New hardware support for multiple Mediatek, Renesas and Samsung
Exynos chips
- Minor updates on Zynq, Qualcomm, Amlogic, TI, Samsung, Nvidia and
Apple chips
There will be a follow up with a few more driver updates that are
still causing build regressions at the moment"
* tag 'soc-drivers-6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (97 commits)
irqchip: Add support for Amlogic A4 and A5 SoCs
dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs
reset: imx: fix incorrect module device table
dt-bindings: power: qcom,kpss-acc-v2: add qcom,msm8916-acc compatible
bus: qcom-ssc-block-bus: Fix the error handling path of qcom_ssc_block_bus_probe()
bus: qcom-ssc-block-bus: Remove some duplicated iounmap() calls
soc: qcom: pd-mapper: Add support for SDM630/636
reset: imx: Add SCU reset driver for i.MX8QXP and i.MX8QM
dt-bindings: firmware: imx: add property reset-controller
dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7
memory: mtk-smi: Add ostd setting for mt8192
dt-bindings: soc: samsung: exynos-usi: Drop unnecessary status from example
firmware: tegra: bpmp: Fix typo in bpmp-abi.h
soc/tegra: pmc: Use str_enable_disable-like helpers
soc: samsung: include linux/array_size.h where needed
firmware: arm_scmi: use ioread64() instead of ioread64_hi_lo()
soc: mediatek: mtk-socinfo: Add extra entry for MT8395AV/ZA Genio 1200
soc: mediatek: mt8188-mmsys: Add support for DSC on VDO0
soc: mediatek: mmsys: Migrate all tables to MMSYS_ROUTE() macro
soc: mediatek: mt8365-mmsys: Fix routing table masks and values
...
|
||
|
Mahesh Rao
|
fbfb649870 |
dt-bindings: firmware: stratix10: Convert to json-schema
Convert intel,stratix10-svc service layer devicetree binding file from freeform format to json-schema. Also added DT binding for optional stratix10-soc FPGA manager child node. Signed-off-by: Mahesh Rao <mahesh.rao@intel.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> |
||
|
Arnd Bergmann
|
29759d2729 |
Reset controller updates for v6.15
* Add missing microchip,sam9x7-rstc compatible to device tree binding documentation. * Add SCU reset driver for i.MX8QXP and i.MX8QM. -----BEGIN PGP SIGNATURE----- iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCZ9RbMRcccC56YWJlbEBw ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwHn0AP9GbWMXwwnx+DKAMYMjeErygVLD q4bAm8h+pqNylxCqngD9HrqzJ5/gbbqMnLJifaBtCutXf4aR2iDzH/uGa1tnewA= =LC08 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmfbPIwACgkQYKtH/8kJ UicNug//cJx5XBsSAzRGDhQhQXBZnw28LS5EceuoAgIZFCTMOU8SafTCjSwj26xv nL6vNqtPGTZc8RrvM2XC457ptDuxKOoNEL8xYYxyIgRu1ZxVzTKS8eo76dY0FiIX kphglhHMR8IPLYsiJIwNYkniqeE58O0jjtMHueSpWcJ6b3MD9wxSeRBA3iSn6j5/ lgQolkHfUZ3+mAyAUdVM1eVtQKGRK97h5et7Q3/Jtk6RyAfu2xtke7ARMudmOfXc DuCRv851pe7zB6trwvAxbldO+62ip6fQ9LKPWA5Mx8MMOH9aLS7kE5jHwEGHdFdv VMcyktyDagzHKtug7KZRjUnhnbTQR+KmoVgU1UbK0AcZC5P9ujmzD9pia5B7Cl1F norarbymUyLs/QJDfnChWRm3VOsKDsO/Tz0yKDgJ9P2uvZwteb6BREHPxgF9oCEC QK7poFnIVvQC+Bjc+P+R10jna37PA3uD+88E8QxKeqGjGrYIfZuIyn/MYdjIM/CI +hOCKqnqOOlDV2+OSdzAccGvEyHpnGLlcHw8jYIk2gjZ8MjWm6llcWS22UPi6Ze2 xtUD2JxaWc4dNK0Ea8wwXcQk01HpS7xZxAVD2p6OCSKWjVSDsd8JDjdJL1UI5e7m MJ0+Y0mm2nxld/zCKH8DRtYTAz8mde7aAKLnLLQ6VTF8q/cVQ8o= =KKCI -----END PGP SIGNATURE----- Merge tag 'reset-for-v6.15' of git://git.pengutronix.de/pza/linux into soc/drivers Reset controller updates for v6.15 * Add missing microchip,sam9x7-rstc compatible to device tree binding documentation. * Add SCU reset driver for i.MX8QXP and i.MX8QM. * tag 'reset-for-v6.15' of git://git.pengutronix.de/pza/linux: reset: imx: fix incorrect module device table reset: imx: Add SCU reset driver for i.MX8QXP and i.MX8QM dt-bindings: firmware: imx: add property reset-controller dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7 Link: https://lore.kernel.org/r/20250314164406.744117-1-p.zabel@pengutronix.de Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Michal Wilczynski
|
fe59b03954 |
dt-bindings: firmware: thead,th1520: Add support for firmware node
The kernel communicates with the E902 core through the mailbox transport using AON firmware protocol. Add dt-bindings to document it the dt node. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Acked-by: Drew Fustini <drew@pdp7.com> Link: https://lore.kernel.org/r/20250311171900.1549916-2-m.wilczynski@samsung.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> |
||
|
Frank Li
|
778752759b |
dt-bindings: firmware: imx: add property reset-controller
System Controller Firmware(SCU) reset some peripherals, such as CSI. So add reset-controller for it. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250210-8qxp_camera-v3-1-324f5105accc@nxp.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Tudor Ambarus
|
97b9ee2972 |
dt-bindings: firmware: add google,gs101-acpm-ipc
Add bindings for the Samsung Exynos ACPM mailbox protocol. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250213-gs101-acpm-v9-1-8b0281b93c8b@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
||
|
Manikanta Mylavarapu
|
6cf5e9a6d2 |
dt-bindings: firmware: qcom,scm: Document ipq5424 SCM
Document the scm compatible for ipq5424 SoC. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20241204133627.1341760-2-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Qingqing Zhou
|
0124b9bebd |
dt-bindings: firmware: qcom,scm: document QCS615 SCM
Add the compatible for Qualcomm QCS615 SCM. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> Link: https://lore.kernel.org/r/20241105032107.9552-2-quic_qqzhou@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Arnd Bergmann
|
1876c788bb |
A few more Qualcomm driver updates for v6.13
Make the Adreno driver invoke the SMMU aperture setup firmware function, which is required to allow the GPU to manage per-process page tables in some firmware versions - as an example Rb3Gen2 has no GPU without this. Add X1E Devkit to the list of devices that has functional EFI variable access through the uefisecapp. Flip the "manual slice configuration quirk" in the Qualcomm LLCC driver, as this only applies to a single platform, and introduce support for QCS8300, QCS615, SAR2130P, and SAR1130P. Lastly, add IPQ5424 and IPQ5404 to the Qualcomm socinfo driver. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmc0G8EVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FNLwP/1g/MKjDI3AT0esqzTvD5AUgpCab Vb20nlK57Qt64k6WdQ8DLVygA7sb9iB5mq/KYSr3k4+S1DdG8qLzRkL0N/uD9Hwv AHEb7pPtuFIFSsV8+o41SPn30lg6AkxkjbGgMUDrT0hvZcBxUzGHRFbs8HM5ShCg i1Sy/eZje+iX8wOF5xW960eMT3e/8FvW145nLi1uYuaCyCh0A/wNpahjtKpA0q6A s3rnhDye6qJQxcd0xk7fYCbc39iBF4D1Jvrog6Mc4TLKdLULnXIPIJxc7NRm8uGw WbhYwNsYmCGkErAorvPtEDacYxi7sFAwMD+ALayBnhnsU/l5Nz44JfZwIqKUg+WJ bsc+kJRT3oIfwfSJO+tBFI80XDCiTb6Wyyn2lemO1L5NQgDMLxFXBo7tadScS2FM /QEYJvZj4SVfG6rpfD/+4ZVw6FjKnkhDTYoB4Q4uqia4GLfZtIl925xJtaNCtQNM nku4sL+HK2HdL1HuZuVE1Uamt62sdzL2iqwctcjoPpIcq+WB8XwPfshg/iO57vao IFVcPUs/enoCU7PtovQWrI+CcVxaZvOOst4M0Pou9DBi3jGLbVdS9/kt7HEFwbD9 qmdydfPZty2lMHvFl5Q6PzfszGf4+78em/dtz5/BUgB2C7Y56427fbbu0g+ADf8w z8Hq5lM++Qh7SwNd =Wqwn -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmc05DAACgkQYKtH/8kJ UidXZQ//b9NHOLIaYNBcxSFT5ibK1orcCpWcUQlzkwKRwz8kXMsXW41t3R/Ab1Wk nJhQFwWL28sDtDTK13mdfSM4dnDuoqtjIk4/40LGyivla7m5LCPr775xFYJzfRPc z0gZvabNp4syKC4l5FCFILOxeYE2cyDkzGMxlTg5ztUfF4AsFr3PrJq9wmvhfQo8 GRm6XSsAaq7cshEwYqJRtDfR3i6vzaqbbn54/HHBTpMZnhus2iZk92Q1gEekD2fi UjySAmdOFCjCIPCxxrRMEPupHjT20DqJVK//m/kNCNAw4i4049o1Xu/KjoymPQNa Wg/UjS5Lsne58dFI1Kmmdat9nqrVrd0ZXQd4mpERSJKYAGptO73PNofzFDvtuLYX V3usgZIZJzk/L+amkVIeY/Ot8fPgiRgb2G5SIcWcIBqiUtwNyw3TOnxcswcml8JA gzneVx4LryrRPrjJGTb1LqefwH4Rs48RpKUVDrHN7vxK3r3EKirqxQtTic7kdrJp GbR0OdkfIcLF3k4uSMDSfKlIB7kcldGdJw8ZJY0Qn4yJr7Uss+N4jk6U8eqkW0AC 0LKGXk4ym9t8rFYnfck/toGDtXMFnjNFnY+SYq9F241Ux08l2stme14PG7Mu0tyY dxEbV1FYkxy55LVYgW0hK/Y5+ogGusNfJICZSTen6NDGK38+x4I= =yuqG -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers A few more Qualcomm driver updates for v6.13 Make the Adreno driver invoke the SMMU aperture setup firmware function, which is required to allow the GPU to manage per-process page tables in some firmware versions - as an example Rb3Gen2 has no GPU without this. Add X1E Devkit to the list of devices that has functional EFI variable access through the uefisecapp. Flip the "manual slice configuration quirk" in the Qualcomm LLCC driver, as this only applies to a single platform, and introduce support for QCS8300, QCS615, SAR2130P, and SAR1130P. Lastly, add IPQ5424 and IPQ5404 to the Qualcomm socinfo driver. * tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: soc: qcom: ice: Remove the device_link field in qcom_ice drm/msm/adreno: Setup SMMU aparture for per-process page table firmware: qcom: scm: Introduce CP_SMMU_APERTURE_ID soc: qcom: socinfo: add IPQ5424/IPQ5404 SoC ID dt-bindings: arm: qcom,ids: add SoC ID for IPQ5424/IPQ5404 soc: qcom: llcc: Flip the manual slice configuration condition dt-bindings: firmware: qcom,scm: Document sm8750 SCM firmware: qcom: uefisecapp: Allow X1E Devkit devices soc: qcom: llcc: Add LLCC configuration for the QCS8300 platform dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC soc: qcom: llcc: Add configuration data for QCS615 dt-bindings: cache: qcom,llcc: Document the QCS615 LLCC soc: qcom: llcc: add support for SAR2130P and SAR1130P soc: qcom: llcc: use deciman integers for bit shift values dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P Link: https://lore.kernel.org/r/20241113032425.356306-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Arnd Bergmann
|
ec72578ef9 |
Arm SCMI updates for v6.13
Just couple of main additions:
1. Support for variable I/O width within ARM SCMI shared memory area.
Some shared memory areas might only support a certain access width,
such as 32-bit, which memcpy_{from,to}_io() does not adhere to at least
on ARM64 by making both 8-bit and 64-bit accesses to such memory.
This support updates the shmem layer to support reading from and
writing to such shared memory area using the specified I/O width
in the Device Tree. The various transport layers making use of the
shmem.c code are updated accordingly to pass the I/O accessors that
they store. The device tree bindings are also updated for the same.
2. Extension of SCMI transport bindings to add more properties
SCMI transports are characterized by a number of properties. The
values assumed by some of them tightly depend on the choices taken at
design time and on the overall archiecture of the specific platform:
things like timeouts, maximum message size and number of in-flight
messages are closely tied to the architecture of the platform like
number of SCMI agents on the system, physical memory available to the
SCMI platform and so on. Such details are not discoverable as they are
outside the scope of the SCMI protocol specification.
Currently such properties are simple default values defined at build
time, but the increasing number and variety of platforms using SCMI
with a wide range of designs has increased the need to have a way to
describe such properties across all these platforms.
Apart from the above two, there is one NULL pointer dereference fix for
very age old SCPI protocol driver which seems to be still in use on few
platforms.
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Merge tag 'scmi-updates-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers
Arm SCMI updates for v6.13
Just couple of main additions:
1. Support for variable I/O width within ARM SCMI shared memory area.
Some shared memory areas might only support a certain access width,
such as 32-bit, which memcpy_{from,to}_io() does not adhere to at least
on ARM64 by making both 8-bit and 64-bit accesses to such memory.
This support updates the shmem layer to support reading from and
writing to such shared memory area using the specified I/O width
in the Device Tree. The various transport layers making use of the
shmem.c code are updated accordingly to pass the I/O accessors that
they store. The device tree bindings are also updated for the same.
2. Extension of SCMI transport bindings to add more properties
SCMI transports are characterized by a number of properties. The
values assumed by some of them tightly depend on the choices taken at
design time and on the overall archiecture of the specific platform:
things like timeouts, maximum message size and number of in-flight
messages are closely tied to the architecture of the platform like
number of SCMI agents on the system, physical memory available to the
SCMI platform and so on. Such details are not discoverable as they are
outside the scope of the SCMI protocol specification.
Currently such properties are simple default values defined at build
time, but the increasing number and variety of platforms using SCMI
with a wide range of designs has increased the need to have a way to
describe such properties across all these platforms.
Apart from the above two, there is one NULL pointer dereference fix for
very age old SCPI protocol driver which seems to be still in use on few
platforms.
* tag 'scmi-updates-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
firmware: arm_scpi: Check the DVFS OPP count returned by the firmware
firmware: arm_scmi: Relocate atomic_threshold to scmi_desc
firmware: arm_scmi: Use max_msg and max_msg_size devicetree properties
dt-bindings: firmware: arm,scmi: Introduce more transport properties
firmware: arm_scmi: Calculate virtio PDU max size dynamically
firmware: arm_scmi: Account for SHMEM memory overhead
firmware: arm_scmi: Support 'reg-io-width' property for shared memory
dt-bindings: sram: Document reg-io-width property
firmware: arm_scmi: Use vendor string in max-rx-timeout-ms
dt-bindings: firmware: arm,scmi: Add missing vendor string
firmware: arm_scmi: Reject clear channel request on A2P
firmware: arm_scmi: Fix slab-use-after-free in scmi_bus_notifier()
Link: https://lore.kernel.org/r/20241106110727.4007489-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||
|
Melody Olvera
|
4cadd10620 |
dt-bindings: firmware: qcom,scm: Document sm8750 SCM
Document the scm compatible for sm8750 SoC. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241021230427.2632466-1-quic_molvera@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Zhenhua Huang
|
fc0dead9b7 |
dt-bindings: firmware: qcom,scm: document SCM on QCS8300 SoCs
Document scm compatible for the Qualcomm QCS8300 SoC. It is an interface to communicate to the secure firmware. Signed-off-by: Zhenhua Huang <quic_zhenhuah@quicinc.com> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20240911-qcs8300_binding-v2-2-de8641b3eaa1@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Nikunj Kela
|
b4bd100500 |
dt-bindings: firmware: qcom,scm: document support for SA8255p
Add a compatible for the SA8255p platform's Secure Channel Manager firmware interface. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com> Link: https://lore.kernel.org/r/20240905183016.3742735-1-quic_nkela@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Cristian Marussi
|
5654d37268 |
dt-bindings: firmware: arm,scmi: Introduce more transport properties
Depending on specific hardware and firmware design choices, it may be possible for different platforms to end up having different requirements regarding the same transport characteristics. Introduce max-msg-size and max-msg properties to describe such platform specific transport constraints, since they cannot be discovered otherwise. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Cristian Marussi <cristian.marussi@arm.com> Message-Id: <20241028120151.1301177-4-cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> |
||
|
Cristian Marussi
|
7bf46ec090 |
dt-bindings: firmware: arm,scmi: Add missing vendor string
Recently introduced max-rx-timeout-ms optionao property is missing a
vendor prefix.
Add the vendor prefix so that it aligns with the new properties that
are about to get added soon.
Fixes:
|
||
|
Dmitry Baryshkov
|
e19bc8b224 |
dt-bindings: firmware: qcom,scm: Add SAR2130P compatible
Document compatible for the SCM firmware interface on SAR2130P platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241017-sar2130p-scm-v1-1-cc74a6b75c94@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Peng Fan
|
7d2b23fda9 |
dt-bindings: firmware: Add i.MX95 SCMI Extension protocol
Add i.MX SCMI Extension protocols bindings for: - Battery Backed Module(BBM) Protocol This contains persistent storage (GPR), an RTC, and the ON/OFF button. The protocol can also provide access to similar functions implemented via external board components. - MISC Protocol. This includes controls that are misc settings/actions that must be exposed from the SM to agents. They are device specific and are usually define to access bit fields in various mix block control modules, IOMUX_GPR, and other GPR/CSR owned by the SM. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Message-Id: <20240823-imx95-bbm-misc-v2-v8-1-e600ed9e9271@nxp.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> |
||
|
Peng Fan
|
3a5e6ab06e |
dt-bindings: firmware: arm,scmi: Introduce property max-rx-timeout-ms
System Controller Management Interface(SCMI) firmwares might have different designs depending on the platform: the maximum receive channel timeout value might vary depending on the specific underlying hardware and firmware design choices. Introduce the general property max-rx-timeout-ms property to describe the transport needs of a specific platform design. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> [Cristian: reworded commit message, s/mailbox/transport in description] Signed-off-by: Cristian Marussi <cristian.marussi@arm.com> Tested-by: Peng Fan <peng.fan@nxp.com> #i.MX95 19x19 EVK Message-Id: <20240730144707.1647025-3-cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> |
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Peng Fan
|
4d5921a39f |
dt-bindings: firmware: arm,scmi: Add support for system power protocol
Add SCMI System Power Protocol bindings, and the protocol id is 0x12. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Message-Id: <20240628030309.1162012-1-peng.fan@oss.nxp.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> |
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Linus Torvalds
|
8e313211f7 |
Pin control bulk changes for the v6.11 kernel series:
Core changes: None. New drivers: - Renesas RZ/V2H(P) SoC - NXP Freescale i.MX91 SoC - Nuvoton MA35D1 SoC - Qualcomm PMC8380, SM4250, SM4250 LPI Enhancements: - A slew of scoped-based simplifications of of_node_put(). -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmacNaMACgkQQRCzN7AZ XXM2zBAApbYm8ftQ0Og6AKEapMUWWQl8eo0TMG4E81vqx9oAs0qDjFvKyHioy/Gm ZKwfmRPFqg/rxWP4eFOCE/dQwL7gELPOIiJJOlV+qF9dUcQo/cdSPze//mt06iTl xRnKL8/r+LlFU2qBcfqzdrqeCV52TZUhRrYlau+9CxGkFTF7KVNQossInMPC91gY aClovH5CDn1pl8SOziGOpPVqv9UJR0KkEDeoroWQ6IcBx3OutAan77KySpJFThcJ ZHN7cNYPgLItmJz7ERXtWumVRM4sRZ0jwQeUE9A+tMuTyhplguKHDeZjRxojoGkM HcYA7WUUrMPNzc9163+7A9qEhMzR6HINFBtysRWuQolofYq44w50/v6DL5xvdOoe 1adJzxH+JiBRWQ4fTq4Gc2QEICY59kmHamOrGLGCqeIldMRC+fQCHF+4mnqMSbru eXuvdXjzPes1KflmaHmb6s2AxJjYLmIdcfsElMAy7uz9hghzPhYUeq0157Fa3Igp M7dK1Wh9lGjudLvEXz6ZW/OV57eOo+Xc7yISVi/OnD+qiMejnzNoEcy83zSa/7sh O/BlbuHOwVv+Gysgs0Fphu9GjZuPuzjT8NyKlzouFgrUE38LojY/Dz1SF1FYJL+9 9t6TbnJnpmPwVMT3p63BmSj5f3iTUXqGd0IPqCZltTc1rPl7X/w= =79pj -----END PGP SIGNATURE----- Merge tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Some new drivers is the main part, the rest is cleanups and nonurgent fixes. Nothing much special about this, no core changes this time. New drivers: - Renesas RZ/V2H(P) SoC - NXP Freescale i.MX91 SoC - Nuvoton MA35D1 SoC - Qualcomm PMC8380, SM4250, SM4250 LPI Enhancements: - A slew of scoped-based simplifications of of_node_put()" * tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits) pinctrl: renesas: rzg2l: Support output enable on RZ/G2L pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions pinctrl: renesas: rzg2l: Clarify OEN read/write support dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range description dt-bindings: pinctrl: npcm8xx: add missing pin group and mux function dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties pinctrl: freescale: Use scope based of_node_put() cleanups pinctrl: equilibrium: Use scope based of_node_put() cleanups pinctrl: ti: iodelay: Use scope based of_node_put() cleanups pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32 pinctrl: cy8c95x0: Update cache modification pinctrl: cy8c95x0: Use cleanup.h pinctrl: renesas: r8a779h0: Remove unneeded separators pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and function pinctrl: renesas: r8a779g0: Remove unneeded separators pinctrl: renesas: r8a779h0: Add AVB MII pins and groups pinctrl: renesas: r8a779g0: Fix TPU suffixes pinctrl: renesas: r8a779g0: Fix TCLK suffixes pinctrl: renesas: r8a779g0: FIX PWM suffixes pinctrl: renesas: r8a779g0: Fix IRQ suffixes ... |
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Arnd Bergmann
|
ee22fbd705 |
Qualcomm driver updates for v6.11
Support for Shared Memory (shm) Bridge is added, which provides a stricter interface for handling of buffers passed to TrustZone. The X1Elite platform is added to uefisecapp allow list, to instantiate the efivars implementation. A new in-kernel implementation of the pd-mapper (or servreg) service is introduced, to replace the userspace dependency for USB Type-C and battery management. Support for sharing interrupts across multiple bwmon instances is added, and a refcount imbalance issue is corrected. The LLCC support for recent platforms is corrected, and SA8775P support is added. A new interface is added to SMEM, to expose "feature codes". One example of the usecase for this is to indicate to the GPU driver which frequencies are available on the given device. The interrupt consumer and provider side of SMP2P is updated to provide more useful names in interrupt stats. Support for using the mailbox binding and driver for outgoing IPC interrupt in the SMSM driver is introduced. socinfo driver learns about SDM670 and IPQ5321, as well as get some updates to the X1E PMICs. pmic_glink is bumped to now support managing 3 USB Type-C ports. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmaHa9UVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FUOYP/1Z2gwAlkGLQsSVGmDAbEAClFyhm JvgBn87fouKQ5pPwbdLLhylxwlkdtCQ/WL9Zm0Ue5wfXmRlLApVrEfBbG9HY4fG7 yTk0u5H0qcln5KqEB9XFxzHfPbjGBKrF5sRfFlTEncQ+/viwu4Jw2BdY9Hs2zCAV 0Qbc7mFVzOYOC+MTil8p0qMAxi/cCnWwi+NCfy7bKgvdW3lzuDrvw3vdwf0TbzwQ asTjjH2+VA3cHqosRx5vhvoO89w2V1JAEEkifu9TtF0j8+FUNql9h8SxMGi3aOqw uXh+lSBLPkSv3aptkqxl7bUX4axtdwPqhvNb4Fe0Z1EaMGZ3v6C/LynTsSwF36H0 fNYu5n1MW9Cl6ypxycSdcJxMbYv9Czy7GkwhTPZPWepvQC+XcjH/VyvzAmyDLpYe UZzYH/6AqT/lCSVQtb+ySML8BObXMZOfIAH2EtoyLw/jlKb2cAWwMXftSD9VgFH0 j0PAM43w2LYgFFy6Cmla4jX9pW2MooEF/3K1GM2rvsQzinZa5+EK1UKpqam5Kq+d h8FakZ6cl86y5pzg6QcVbm2pxKpAGFjArzpHKshLMp9Krkjhfopyl3tN7aXG3VOF qSeWdEP2TAUyQFGJNuUxeb7PZc+VdBHBPmaGDFhaLy+J1Huu8kc3TQuAkxxpXXIj /vpF+Aeyl14J1lQS =Eknv -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmaM/jYACgkQYKtH/8kJ UieyzBAAjEB2YIKZzlt/OFca+NG3zYlnt2rYxjW0Jc4wI/LaJn6fshQ/fExjvUqB lfYIn5rLVXsB29+Xc1fK8rGEp5N2AtY5syAr2Ji44EXheCNa5HsxkLVS9K6bjUvr ljJYo23Gr3S9XnkClGVxuZX7QfS0DUPSr1mo4kJXiNhUg++YDTG6A0z/Njo/LziO pzSmc8vG0pPGG+B5GNwiQO2KW8ZFgT6L0A8neLIcols3o0Vcnce6MnT+OHpRFbjx bEvo9I/JbKFRRzYzztTb2Qtl3tzo230K/D5/8oaLKkLj7FZrULudrPYs0nT4l8tN qN/8gqsKxKTqPxFgQlSIT9G+14OqsKWcLs4qTNnZUsVweIoCnWj2IEkXY6C4KOHX 1LHTucglBK7LwBxBtbjE6bNwGuMnaZJycc9UDmDcGzuhEhFpUH6Jp6NG8Jf8xv7L Ua1JJbF4cnAFQMOxkukYqxu2G7j3qmK4irsoVUJDZsl6ZY3Qn7itkpsKCw24Gspz HvAASOp1wpkz4aFCR61kPOubsKKWMTe0zOTCDPHqeMX+PrjfH9nkuXCw0N44zlHB VuCl5yqVnWmmKbxZ5ahFgogZBu5gLF5LtMgLQAD2zzL01JT1kZydFtGvh5/uVdDC 8yym+fdL7UeolocK9Qj6M1KKfpiLr2OYGuk9ONG7E/9yknOfDJk= =lPdX -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v6.11 Support for Shared Memory (shm) Bridge is added, which provides a stricter interface for handling of buffers passed to TrustZone. The X1Elite platform is added to uefisecapp allow list, to instantiate the efivars implementation. A new in-kernel implementation of the pd-mapper (or servreg) service is introduced, to replace the userspace dependency for USB Type-C and battery management. Support for sharing interrupts across multiple bwmon instances is added, and a refcount imbalance issue is corrected. The LLCC support for recent platforms is corrected, and SA8775P support is added. A new interface is added to SMEM, to expose "feature codes". One example of the usecase for this is to indicate to the GPU driver which frequencies are available on the given device. The interrupt consumer and provider side of SMP2P is updated to provide more useful names in interrupt stats. Support for using the mailbox binding and driver for outgoing IPC interrupt in the SMSM driver is introduced. socinfo driver learns about SDM670 and IPQ5321, as well as get some updates to the X1E PMICs. pmic_glink is bumped to now support managing 3 USB Type-C ports. * tag 'qcom-drivers-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (48 commits) soc: qcom: smp2p: Use devname for interrupt descriptions soc: qcom: smsm: Add missing mailbox dependency to Kconfig soc: qcom: add missing pd-mapper dependencies soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances dt-bindings: interconnect: qcom,msm8998-bwmon: Add X1E80100 BWMON instances dt-bindings: interconnect: qcom,msm8998-bwmon: Remove opp-table from the required list firmware: qcom: tzmem: export devm_qcom_tzmem_pool_new() soc: qcom: add pd-mapper implementation soc: qcom: pdr: extract PDR message marshalling data soc: qcom: pdr: fix parsing of domains lists soc: qcom: pdr: protect locator_addr with the main mutex firmware: qcom: scm: clarify the comment in qcom_scm_pas_init_image() firmware: qcom: scm: add support for SHM bridge memory carveout firmware: qcom: tzmem: enable SHM Bridge support firmware: qcom: scm: add support for SHM bridge operations firmware: qcom: qseecom: convert to using the TZ allocator firmware: qcom: scm: make qcom_scm_qseecom_app_get_id() use the TZ allocator firmware: qcom: scm: make qcom_scm_lmh_dcvsh() use the TZ allocator firmware: qcom: scm: make qcom_scm_ice_set_key() use the TZ allocator firmware: qcom: scm: make qcom_scm_assign_mem() use the TZ allocator ... Link: https://lore.kernel.org/r/20240705034410.13968-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Marek Behún
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f5e6f47f2a
|
dt-bindings: firmware: add cznic,turris-omnia-mcu binding
Add binding for cznic,turris-omnia-mcu, the device-tree node representing the system-controller features provided by the MCU on the Turris Omnia router. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andy Shevchenko <andy@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240701113010.16447-2-kabel@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Bartosz Golaszewski
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9164d2be21 |
dt-bindings: firmware: qcom,scm: add memory-region for sa8775p
Document a new property (currently only for sa8775p) that describes the memory region reserved for communicating with the TrustZone. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20240527-shm-bridge-v10-1-ce7afaa58d3a@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Peng Fan
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997f2cdea3 |
dt-bindings: firmware: arm,scmi: Add properties for i.MX95 Pinctrl OEM extensions
i.MX95 Pinctrl is managed by System Control Management Interface(SCMI) firmware using OEM extensions. No functions, no groups are provided by the firmware. So add i.MX95 specific properties. To keep aligned with current i.MX pinctrl bindings, still use "fsl,pins" for i.MX95. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20240521-pinctrl-scmi-imx95-v1-1-9a1175d735fd@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
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Peng Fan
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d0398f51ff |
dt-bindings: firmware: arm,scmi: Add support for notification completion channel
Per System Control Management Interface specification: "Completion interrupts: This transport supports polling or interrupt driven modes of communication. In interrupt mode, when the callee completes processing a message, it raises an interrupt to the caller. Hardware support for completion interrupts is optional." So, add an optional mailbox channel for notification completion interrupts. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240510-scmi-notify-v2-1-e994cf14ef86@nxp.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> |
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Peng Fan
|
1b403075e6 |
dt-bindings: firmware: Support SCMI pinctrl protocol
Add SCMI v3.2 pinctrl protocol bindings with an example. Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20240418-pinctrl-scmi-v11-2-499dca9864a7@nxp.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> |
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Ulf Hansson
|
4625810361 |
dt-bindings: firmware: arm,scmi: Update examples for protocol@13
Recently we extended the binding for protocol@13 to allow it to be modelled as a generic performance domain. In a way to promote using the new binding, let's update the examples. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240403111106.1110940-1-ulf.hansson@linaro.org Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> |
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Michal Simek
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d8764d347b |
dt-bindings: firmware: xilinx: Describe soc-nvmem subnode
Describe soc-nvmem subnode as the part of firmware node. The name can't be pure nvmem because dt-schema already defines it as array property that's why different name should be used. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/24fe6adbf2424360618e8f5ca541ebfd8bb0723e.1706692641.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
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Michal Simek
|
e83e3c55e4 |
dt-bindings: firmware: xilinx: Sort node names (clock-controller)
Nodes should be sorted that's why move clock-controller to the top of list. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/ccb6bd5f4d1d28983c73497ada596e893fece499.1703161663.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
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Michal Simek
|
6f9c4e691f |
dt-bindings: firmware: xilinx: Describe missing child nodes
Firmware node has more than fpga, aes and clock child nodes but also power, reset, gpio, pinctrl and pcap which are not described yet. All of them have binding in separate files but there is missing connection to firmware node that's why describe it. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1d7988cfadf3554d11f0779f96a670b4fd86ce5a.1703161663.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
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Michal Simek
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93b7a95f6d |
dt-bindings: firmware: xilinx: Fix versal-fpga node name
Based on commit
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Jay Buddhabhatti
|
8e312baacc |
dt-bindings: firmware: versal: add versal-net compatible string
Add dt-binding documentation for Versal NET platforms. Versal Net is a new AMD/Xilinx SoC. The SoC and its architecture is based on the Versal ACAP device. The Versal Net device includes more security features in the platform management controller (PMC) and increases the number of CPUs in the application processing unit (APU) and the real-time processing unit (RPU). Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1705406326-2947516-1-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
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Linus Torvalds
|
c736c9a955 |
Only a couple new SoCs have support added this time, primarily for Qualcomm
SM8650 based on the diffstat. Otherwise this is a collection of non-critical
fixes and cleanups to various clk drivers and their DT bindings. Nothing is
changed in the core clk framework this time, although there's a patch to fix a
basic clk type initialization function. In general, this pile looks to be on
the smaller side.
New Drivers:
- Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650
- Mediatek MT7988 SoC clocks
Updates:
- Update Zynqmp driver for Versal NET platforms
- Add clk driver for Versal clocking wizard IP
- Support for stm32mp25 clks
- Add glitch free PLL setting support to si5351 clk driver
- Add DSI clocks on Amlogic g12/sm1
- Add CSI and ISP clocks on Amlogic g12/sm1
- Document bindings for i.MX93 ANATOP clock driver
- Free clk_node in i.MX SCU driver for resource with different owner
- Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15
- Fix the name of the fvco in i.MX pll14xx by renaming it to fout
- Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC
- Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S
- Check reset monitor registers on Renesas RZ/G2L-alike SoCs
- Reuse reset functionality in the Renesas RZ/G2L clock driver
- Global and RPMh clock support for the Qualcomm X1E80100 SoC
- Support for the Stromer APCS PLL found in Qualcomm IPQ5018
- Add a new type of branch clock, with support for controlling separate
memory control bits, to the Qualcomm clk driver
- Use above new branch type in Qualcomm ECPRI clk driver for QDU1000 and
QRU1000
- Add a number of missing clocks related to CSI2 on Qualcomm MSM8939
- Add support for the camera clock controller on Qualcomm SC8280XP
- Correct PLL configuration in GPU and video clock controllers for
Qualcomm SM8150
- Add runtime PM support and a few missing resets to Qualcomm SM8150
video clock controller
- Fix configuration of various GCC GDSCs on Qualcomm SM8550
- Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver
- Fix up GPU and display clock controllers PLL configuration settings
on Qualcomm SM8550
- Cleanup variable init in Allwinner nkm module
- Convert various DT bindings to YAML
- A few kernel-doc fixes for Samsung SoC clock controllers
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Only a couple new SoCs have support added this time, primarily for
Qualcomm SM8650 based on the diffstat. Otherwise this is a collection
of non-critical fixes and cleanups to various clk drivers and their DT
bindings.
Nothing is changed in the core clk framework this time, although
there's a patch to fix a basic clk type initialization function. In
general, this pile looks to be on the smaller side.
New Drivers:
- Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650
- Mediatek MT7988 SoC clocks
Updates:
- Update Zynqmp driver for Versal NET platforms
- Add clk driver for Versal clocking wizard IP
- Support for stm32mp25 clks
- Add glitch free PLL setting support to si5351 clk driver
- Add DSI clocks on Amlogic g12/sm1
- Add CSI and ISP clocks on Amlogic g12/sm1
- Document bindings for i.MX93 ANATOP clock driver
- Free clk_node in i.MX SCU driver for resource with different owner
- Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15
- Fix the name of the fvco in i.MX pll14xx by renaming it to fout
- Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC
- Add interrupt controller and Ethernet clocks and resets on Renesas
RZ/G3S
- Check reset monitor registers on Renesas RZ/G2L-alike SoCs
- Reuse reset functionality in the Renesas RZ/G2L clock driver
- Global and RPMh clock support for the Qualcomm X1E80100 SoC
- Support for the Stromer APCS PLL found in Qualcomm IPQ5018
- Add a new type of branch clock, with support for controlling
separate memory control bits, to the Qualcomm clk driver
- Use above new branch type in Qualcomm ECPRI clk driver for QDU1000
and QRU1000
- Add a number of missing clocks related to CSI2 on Qualcomm MSM8939
- Add support for the camera clock controller on Qualcomm SC8280XP
- Correct PLL configuration in GPU and video clock controllers for
Qualcomm SM8150
- Add runtime PM support and a few missing resets to Qualcomm SM8150
video clock controller
- Fix configuration of various GCC GDSCs on Qualcomm SM8550
- Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver
- Fix up GPU and display clock controllers PLL configuration settings
on Qualcomm SM8550
- Cleanup variable init in Allwinner nkm module
- Convert various DT bindings to YAML
- A few kernel-doc fixes for Samsung SoC clock controllers"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits)
clk: mediatek: add drivers for MT7988 SoC
clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
dt-bindings: clock: mediatek: add clock controllers of MT7988
dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs
dt-bindings: clock: mediatek: add MT7988 clock IDs
clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes
clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes
clk: mediatek: clk-mux: Support custom parent indices for muxes
dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC
clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx
clk: starfive: Add flags argument to JH71X0__MUX macro
clk: imx: pll14xx: change naming of fvco to fout
clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks
clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu()
clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw
clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config
clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config
clk: qcom: dispcc-sm8550: Use the correct PLL configuration function
clk: qcom: dispcc-sm8550: Update disp PLL settings
clk: qcom: gpucc-sm8550: Update GPU PLL settings
...
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Shubhrajyoti Datta
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39118392d1 |
dt-bindings: Remove alt_ref from versal
The alt_ref is present only in Versal-net devices.
Other versal devices do not have it. So remove alt_ref
for versal.
Fixes:
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Konrad Dybcio
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56fdc35ef0 |
dt-bindings: firmware: qcom,scm: Allow interconnect for everyone
Every Qualcomm SoC physically has a "CRYPTO0<->DDR" interconnect lane. Allow this property to be present, no matter the SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231125-topic-rb1_feat-v3-4-4cbb567743bb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Sibi Sankar
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696945e427 |
dt-bindings: firmware: qcom,scm: document SCM on X1E80100 SoCs
Document scm compatible for X1E80100 SoCs. Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Guru Das Srinagesh <quic_gurus@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231124100608.29964-5-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Neil Armstrong
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6da02af3f9 |
dt-bindings: firmware: qcom,scm: document SM8650 SCM Firmware Interface
Document the SCM Firmware Interface on the SM8650 Platform. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-bindings-scm-v1-1-f687b5aa3c9e@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Arnd Bergmann
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57e06f8c1f |
Qualcomm driver updates for v6.7
This introduces partial support for the Qualcomm Secure Execution Environment SCM interface, and uses this to implement EFI variable access on the Windows On Snapdragon devices (for now). The 32/64-bit calling convention detector of the SCM interface is updated to not choose 64-bit convention when Linux is 32-bit. The "extern" specifier is dropped from the interface include file. The LLCC driver gains support for carrying configuration for multiple different system/DDR configurations for a given platform, and selecting between them. Support for Q[DR]U1000 is added to the driver. All exported symbols are transitioned to EXPORT_SYMBOL_GPL(). The platform_drivers in the Qualcomm SoC are transitioned to the void-returning remove_new implementation. The rmtfs memory driver gains support for leaving guard pages around the used area, to avoid issues if the allocation happens to be placed adjacent to another protected memory region. The socinfo driver gains knowledge about IPQ8174, QCM6490, SM7150P and various PMICs used together with SM8550. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmUsTdwVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FffsQAMcY5NKBZqbQu5wNr2zPnKW5m/30 lYi4bW42mlY6Mo3h97LLxjGM9bqsmPasfAxv/84viN0JYxrSVye/zNtD35qTQBtu t8O8vdOaOYXIc8dwqC16Fl0kI5pm9tl7p5SJmGAUZBvIGUIGngy3gZOYM+HzyMQr UXFO6dO0tQvjowd1t0xE51UNm4J79Vm8HjtuR1pc4i+fZhsy5XhZYq9e4531Yc7o lNacBugjXhurw/rz0odNuRzKn+He+7KQR/hSNv8B2MbH0ZUP+k4VUaRSD9TZyBgC cOahbCfVLkGwepPFGuaaJUUgo8/aa4HiAbdyOrNL2ozYkoLv/PbRrLF0R9KgXK5v LPXpqXt97+rWPnq2iPrfZlo4LAj6JVSCUCxIRZFcWyDFv+wHsYuRbO64s1+MC7+M CPpvup31PLGCeR9Joo/WTt9iAUPJ4BY9v4mkjIdmJF371WRryP4um5Ln6xMC+fIe U/Ss8mPNpSM+guDo8LbdCGAcxWTDk8TOXxa/888y/4Q5Mg97nn0hY2KK4JBmJ7I3 Thd0n9vXjM3oOwPGLC7Y2zj9ZQI5k7JKn331yPS4Hb20SKGEztlaJp4B1DdA5/ul 4BUoh3HWV7dB4l+felrAmPAzAUXvyfGrDBJhXe2dabRJjMhouQ6Wudn3OlC4VP/l fjszjVvPFt7CE30C =B1Kn -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmUv9yoACgkQYKtH/8kJ UifTOQ/+NUj5Y/sAZfMLY3Q3e8s2nsKZLHHUCH7O/DOR6ILc5DZcTI5a23kfIA9V VVluTEnRUzbSHCb3WPW3Yfgy5HpZoaLgXWXGgCsRVKRIODN745TOm2Hn/dFZF0Z7 Fso0oPplGKrvuxSlaxg+1fbJ7c5r8kE/TDu+ok0eiZGvzwfnVas4bB+27thdH/le tY/wS9BhHmBrs6k7gqCfEFWF7M6kS29FOPILIlAfxgUevgSIvAUMBH/KUAGw1Qo/ UNd372TwXkdw0pG2KOx8xR4iKFBfWX4PbHBtBbUZzAnqerDnNrh7p0qTlhfKXOpb jQWx3eqQIwFbbWZ39DxiLE8/h5ig3jF29u1s/vAG2Zb5o5cYwiRM7OjWW8Q8Ha1E ha2NSWMEaNniegnMeoy1VTN8uSYY+dUseKmLmP5vCobmYVKuX96iQx5pNBYhsrwN YOlkOkF1fXINFqSD5v2N4s4AdGx634GgP7azkjm6fGS+hlwKgWNzwH4HHgXNx/u/ IPRPw7U/hji2R++oNPtEOlNHoHWM6Zx0ema38qGTC69uAFHETxbFUmOBaX6q/7Ot AwpP25YozehwDoUVZRwR6CpHcVbKDl4oJhWaruflkxC+6YFTGYS2hPFiF6zbnQw9 u36QDkgNzhBG2LINlmqCAAoGWmC+mqwsqYN/DyKsUUSVEODyUng= =7XXT -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v6.7 This introduces partial support for the Qualcomm Secure Execution Environment SCM interface, and uses this to implement EFI variable access on the Windows On Snapdragon devices (for now). The 32/64-bit calling convention detector of the SCM interface is updated to not choose 64-bit convention when Linux is 32-bit. The "extern" specifier is dropped from the interface include file. The LLCC driver gains support for carrying configuration for multiple different system/DDR configurations for a given platform, and selecting between them. Support for Q[DR]U1000 is added to the driver. All exported symbols are transitioned to EXPORT_SYMBOL_GPL(). The platform_drivers in the Qualcomm SoC are transitioned to the void-returning remove_new implementation. The rmtfs memory driver gains support for leaving guard pages around the used area, to avoid issues if the allocation happens to be placed adjacent to another protected memory region. The socinfo driver gains knowledge about IPQ8174, QCM6490, SM7150P and various PMICs used together with SM8550. * tag 'qcom-drivers-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (44 commits) soc: qcom: socinfo: Convert to platform remove callback returning void soc: qcom: smsm: Convert to platform remove callback returning void soc: qcom: smp2p: Convert to platform remove callback returning void soc: qcom: smem: Convert to platform remove callback returning void soc: qcom: rmtfs_mem: Convert to platform remove callback returning void soc: qcom: qcom_stats: Convert to platform remove callback returning void soc: qcom: qcom_gsbi: Convert to platform remove callback returning void soc: qcom: qcom_aoss: Convert to platform remove callback returning void soc: qcom: pmic_glink: Convert to platform remove callback returning void soc: qcom: ocmem: Convert to platform remove callback returning void soc: qcom: llcc-qcom: Convert to platform remove callback returning void soc: qcom: icc-bwmon: Convert to platform remove callback returning void firmware: qcom_scm: use 64-bit calling convention only when client is 64-bit soc: qcom: llcc: Handle a second device without data corruption soc: qcom: Switch to EXPORT_SYMBOL_GPL() soc: qcom: smem: Annotate struct qcom_smem with __counted_by soc: qcom: rmtfs: Support discarding guard pages dt-bindings: reserved-memory: rmtfs: Allow guard pages dt-bindings: firmware: qcom,scm: document IPQ5018 compatible firmware: qcom_scm: disable SDI if required ... Link: https://lore.kernel.org/r/20231015204014.855672-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |