Commit Graph

5 Commits

Author SHA1 Message Date
John Ernberg
2df6ee328c dt-bindings: crypto: fsl,sec-v4.0: Add power domains for iMX8QM and iMX8QXP
NXP SoCs like the iMX8QM, iMX8QXP or iMX8DXP use power domains for
resource management.

Add compatible strings for these SoCs (QXP and DXP gets to share as their
only difference is a core-count, Q=Quad core and D=Dual core), and allow
power-domains for them only. Keep the old restriction for others.

Signed-off-by: John Ernberg <john.ernberg@actia.se>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-06-23 16:59:38 +08:00
Rob Herring (Arm)
7686133408 dt-bindings: crypto: fsl,sec-v4.0: Add fsl,sec-v6.0
The fsl,sec-v6.0 binding is the same as the fsl,sec-v4.0 binding, so add
it to the existing schema and drop the old .txt binding.

The compatibles in the .txt binding don't match the 1 user. Follow the
user for the schema.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-05-19 13:48:19 +08:00
Rob Herring (Arm)
61a6ba233f dt-bindings: Unify "fsl,liodn" type definitions
The type definition of "fsl,liodn" is defined as uint32 in
crypto/fsl,sec-v4.0.yaml and uint32-array in soc/fsl/fsl,bman.yaml,
soc/fsl/fsl,qman-portal.yaml, and soc/fsl/fsl,qman.yaml. Unify the type to
be uint32-array and constraint the single entry cases.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241113225614.1782862-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2024-11-27 09:24:23 -06:00
Frank Li
c7de6ee3d3 dt-bindings: crypto: fsl,sec-v4.0: add second register space for rtic
Add two description for register space of rtic. There are two register
space, one is for control and status, the other optional space is
recoverable error indication register space.

Fix below CHECK_DTBS error:
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dtb: crypto@1700000: rtic@60000:reg: [[393216, 256], [396800, 24]] is too long
        from schema $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-08-30 18:22:31 +08:00
Rob Herring
0415d5a010 dt-bindings: crypto: fsl,sec-v4.0: Convert to DT schema
Convert Freescale CAAM/SEC4 binding to DT schema format. The
'fsl,sec-v4.0' and 'fsl,sec-v4.0-mon' parts are independent, so split
them into separate schema files.

Add a bunch of missing compatibles for v5.0, v5.4, etc. Drop unused
'ranges', '#address-cells', and '#size-cells' from fsl,sec-v4.0-mon nodes.

There's one DTB warning for LS1012a which has a 2nd 'reg' entry for
'fsl,sec-v4.0-rtic'. Leaving that as there is no clue as to what it is for.

Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20230220213334.353779-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
2023-03-17 16:31:20 -05:00