Convert the TI OMAP DES binding to DT schema format.
Drop "ti,hwmods" as it is not actually used for this binding. Only
OMAP2 platforms are using it.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Convert the TI OMAP AES binding to DT schema format. It's a straight
forward conversion.
Make "ti,hwmods" not required as it is deprecated and only used on
OMAP2.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add DT bindings for SAMA7D65 SoC Atmel TDES.
The SAMA7D65 SoC has the same capability as the SAM9x75 SoC.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add DT bindings for SAMA7D65 SoC Atmel SHA.
The SAMA7D65 similar to the SAM9x75 SoC supports SHA1/224/256/384/512
and supports HMAC for the same hashes. They both also support automatic
padding as well as double buffering.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add DT bindings for SAMA7D65 SoC in atmel AES.
The SAMA7D65 similar to the SAM9x75 SoC supports HMAC, dual buffer, and
GCM. And similar all 3 it supports CBC, CFB, CTR, ECB, and XTS.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
NXP SoCs like the iMX8QM, iMX8QXP or iMX8DXP use power domains for
resource management.
Add compatible strings for these SoCs (QXP and DXP gets to share as their
only difference is a core-count, Q=Quad core and D=Dual core), and allow
power-domains for them only. Keep the old restriction for others.
Signed-off-by: John Ernberg <john.ernberg@actia.se>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
- support for game controllers requiring delayed initialization
packets, such as ByoWave Proteus, in xpad driver
- a change to atkbd driver to not reset the keyboard on Loongson devices
- tweaks to gpio-keys and matrix_keypad drivers
- fixes to documentation for Amiga joysticks
- a fix to ims-pcu driver to better handle malformed firmware.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQST2eWILY88ieB2DOtAj56VGEWXnAUCaD0unwAKCRBAj56VGEWX
nOfoAQCX4WWJumaFu9wAix2cdu+zfNNmqvtOZu0rWrs0ah8NzgD/VGLoemFf3gg3
SjetSN3yHI5XUicvs2Jcydts7n3GMgI=
=32Le
-----END PGP SIGNATURE-----
Merge tag 'input-for-v6.16-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
Pull input updates from Dmitry Torokhov:
- support for game controllers requiring delayed initialization
packets, such as ByoWave Proteus, in xpad driver
- a change to atkbd driver to not reset the keyboard on Loongson
devices
- tweaks to gpio-keys and matrix_keypad drivers
- fixes to documentation for Amiga joysticks
- a fix to ims-pcu driver to better handle malformed firmware
* tag 'input-for-v6.16-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input:
Input: ims-pcu - check record size in ims_pcu_flash_firmware()
Input: gpio-keys - fix possible concurrent access in gpio_keys_irq_timer()
Input: gpio-keys - fix a sleep while atomic with PREEMPT_RT
Input: amijoy - make headings compliant w/ guidelines in documentation
Input: amijoy - fix grammar in documentation
Input: amijoy - fix Amiga 4-joystick adapter pinout in documentation
Input: amijoy - fix broken table formatting in documentation
Input: atkbd - do not reset keyboard by default on Loongson
Input: xpad - send LED and auth done packets to all Xbox One controllers
Input: xpad - add the ByoWave Proteus controller
Input: xpad - allow delaying init packets
MAINTAINERS: update dlg,da72??.txt to yaml
dt-bindings: input: convert dlg,da7280.txt to dt-schema
dt-bindings: input: touchscreen: edt-ft5x06: use unevaluatedProperties
Input: snvs_pwrkey - support power-off-time-sec
dt-bindings: crypto: fsl,sec-v4.0-mon: Add "power-off-time-sec"
Input: matrix_keypad - detect change during scan
Input: matrix_keypad - add function for reading row state
Convert the Marvell CESA binding to DT schema format. The
marvell-cesa.txt and mv_cesa.txt are duplicate bindings.
The clock properties are quite varied for each platform hence the
if/then schemas. The old binding was fairly accurate with reality.
The original binding didn't mention there is 1 interrupt per CESA
engine. Based on users, there's a maximum of 2 engines.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Convert the HiSilicon HIP06/7 Security Accelerator binding to DT schema
format. It's a straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Convert the Broadcom SPUM/SPU2 binding to DT schema format. It's a
straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Convert the Axis Crypto engine binding to DT schema format. It's a
straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Convert the AMD Cryptographic Coprocessor binding to DT schema format.
It's a straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The mediatek,eip97-crypto binding is half abandoned. The driver was
dropped in 2020 as the Mediatek platforms use InsideSecure block and
the driver for it. All the platforms except MT7623 were updated. A
patch to update it was submitted, but never addressed the review
comments.
Link: https://lore.kernel.org/all/20210303080923.16761-1-vic.wu@mediatek.com/
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The fsl,sec-v6.0 binding is the same as the fsl,sec-v4.0 binding, so add
it to the existing schema and drop the old .txt binding.
The compatibles in the .txt binding don't match the 1 user. Follow the
user for the schema.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
-----BEGIN PGP SIGNATURE-----
iQFSBAABCgA8FiEEq68RxlopcLEwq+PEeb4+QwBBGIYFAmghHIMeHHRvcnZhbGRz
QGxpbnV4LWZvdW5kYXRpb24ub3JnAAoJEHm+PkMAQRiGQP4H/0nzYeRJaWdhar4B
tb3tOUyHpokhqNpWYA+fSxq83H1yTuxv3PoHDJg1OEXfmwmfKS8+UelkBZX+fl/q
gfUz9CdmgMfXyXHw3jQnDGx6IwBDT5z3GfKbmFyzft8vqMyfGSGYmfdSaR+MZrD6
WxxCyNgPWGkT41MgvHW8JAH8Hj+yyzpu7uqx3LIS2KA3dJcxZGJUYC3uA2UBIuGD
CmTuWaG6zY4uTtiAOXUscKyA9wCh7cawTLJKAtc6SEpzAbMmZ3nUiOAVoKf70R0t
EqH16aToV+th/zUvCuPKT3bWIkiNxDsibtwfW9fIJ8aZnQuvO/bK4ygHXjy8C/vc
PUaWMIA=
=evf8
-----END PGP SIGNATURE-----
Merge tag 'v6.15-rc6' into next
Sync up with mainline to bring in xpad controller changes.
Update to reference the input.yaml schema, thus enabling the use of the
common 'power-off-time' property.
The hardware supports one of four fixed values, and the new property is
optional.
Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250315093455.1100-2-ian.ray@gehealthcare.com
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Document the crypto engine on the QCS615 platform.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Abhinaba Rakshit <quic_arakshit@quicinc.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Document QCS615 compatible for True Random Number Generator.
Signed-off-by: Abhinaba Rakshit <quic_arakshit@quicinc.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Some platforms like Marvell are cache coherent, so allow the
"dma-coherent" property.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Convert the Freescale security engine (crypto accelerator) binding from
text form to YAML. The list of compatible strings reflects what was
previously described in prose; not all combinations occur in existing
devicetrees.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Document the crypto engine on the X1E80100 Platform.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add bindings for the Inside Secure SafeXcel EIP-93 crypto engine.
The IP is present on Airoha SoC and on various Mediatek devices and
other SoC under different names like mtk-eip93 or PKTE.
All the compatible that currently doesn't have any user are defined but
rejected waiting for an actual device that makes use of them.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
- Share a helper to convert from crypto_profile to mmc_host
- Respect quirk_max_rate for non-UHS SDIO card too
MMC host:
- Add DT bindings for the mmc-slot
- Clarify DT bindings for the mmc-controller
- bcm2835: Add support for system-wide suspend/resume PM
- dw_mmc-exynos: Add support for the exynos8895 variant
- meson-mx-sdio: Convert DT bindings to dtschema
- mtk-sd: Fixup use of two register ranges
- mtk-sd: Add support for ignoring cmd response CRC
- sdhci-esdhc-imx: enable 'SDHCI_QUIRK_NO_LED' quirk for S32G
- sdhci-msm: Correctly set the load for the regulator
- sdhci-msm: Convert to use custom crypto profile
- sdhci-of-at91: Add support for the microchip sama7d65 variant
-----BEGIN PGP SIGNATURE-----
iQJLBAABCgA1FiEEugLDXPmKSktSkQsV/iaEJXNYjCkFAmeOYOYXHHVsZi5oYW5z
c29uQGxpbmFyby5vcmcACgkQ/iaEJXNYjClhzxAAsytG5oxMbCNEbLV00CqX58n3
BJTpDVaG6CYy+pr6lgNBljswl1kzX36sHuBsD6nUve8ZP145UU3PC8tEgdYTDzx1
oLog+ObTTkHlVK2X9XWfhuv6EDhqBN5z3Z43yKVCAfFgti/amSgevv1DKJSZ5Q3W
4ybo/4sttXL2PaShLkAUnm+w50Iq+D7i2vq6mvXyw90vsS/wvO//hljW3tLTKA5G
Xsb3jNZt48F+AKFrIbB2V2c2SgiyyCR+po+5ZGCAIPwwC/SCJBjkmDzPd0+5aAVU
HQudyUC6vdB/gODYJtsyV4q5YHOLqP4hLaN46hwD0SZHmQPgTIMxOlQCZDUqxwUn
GlZsN5nBwEl+eKVDiiiS3b8wO0geXjUVvw5+qvb1mXeHULBFlYxksJGE+eUfrW9D
ldouNLggHN6gtIFlPIS98D3ly2WPBGC/xMs3pvWaOK+hMeH1IpjZw+b8kcuojVIh
7mODdyxZGGaqGyhaWQHvwtHgGJKMbqm5sr2amVZkoChgNysomGpR/bMvBpv0HMC8
oUTGF8CaC8W4auTc6Jx7NtdAaHtPY9URN6Cdyuc8JeBDuKpG9B1m50lrUW3f3PZu
7njzBMdUQ+IBZ5WyimM06qREyFVQEJHiNVb1EnPTWctPoKVj1ZKmS5QeEOYUbUWi
9sC4TwrD2N2Rpuvl5MU=
=KHab
-----END PGP SIGNATURE-----
Merge tag 'mmc-v6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull MMC updates from Ulf Hansson:
"MMC core:
- Share a helper to convert from crypto_profile to mmc_host
- Respect quirk_max_rate for non-UHS SDIO card too
MMC host:
- Add DT bindings for the mmc-slot
- Clarify DT bindings for the mmc-controller
- bcm2835: Add support for system-wide suspend/resume PM
- dw_mmc-exynos: Add support for the exynos8895 variant
- meson-mx-sdio: Convert DT bindings to dtschema
- mtk-sd: Fixup use of two register ranges
- mtk-sd: Add support for ignoring cmd response CRC
- sdhci-esdhc-imx: enable 'SDHCI_QUIRK_NO_LED' quirk for S32G
- sdhci-msm: Correctly set the load for the regulator
- sdhci-msm: Convert to use custom crypto profile
- sdhci-of-at91: Add support for the microchip sama7d65 variant"
* tag 'mmc-v6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (25 commits)
mmc: sdhci-msm: Correctly set the load for the regulator
mmc: hi3798mv200: Use syscon_regmap_lookup_by_phandle_args
mmc: Use of_property_present() for non-boolean properties
dt-bindings: mmc: samsung,exynos-dw-mshc: add specific compatible for exynos8895
mmc: sdhci-msm: convert to use custom crypto profile
mmc: crypto: add mmc_from_crypto_profile()
mmc: mtk-sd: Limit getting top_base to SoCs that require it
dt-bindings: mmc: mtk-sd: Document compatibles that need two register ranges
mmc: sdhci-acpi: Use devm_platform_ioremap_resource()
mmc: sdhci-acpi: Remove not so useful error message
dt-bindings: mmc: convert amlogic,meson-mx-sdio.txt to dtschema
dt-bindings: mmc: document mmc-slot
dt-bindings: mmc: controller: remove '|' when not needed
dt-bindings: mmc: controller: move properties common with slot out to mmc-controller-common
dt-bindings: mmc: controller: clarify the address-cells description
mmc: bcm2835: add suspend/resume pm support
dt-bindings: Drop Bhupesh Sharma from maintainers
mmc: core: don't include 'pm_wakeup.h' directly
mmc: mtk-sd: Add support for ignoring cmd response CRC
mmc: core: Introduce the MMC_RSP_R1B_NO_CRC response
...
Document SM8750 compatible for the True Random Number Generator.
Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Document the crypto engine on the SM8750 Platform.
Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Document ipq9574, ipq5424 and ipq5322 compatible for the True Random Number
Generator.
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
For more than a year all emails to Bhupesh Sharma's Linaro emails bounce
and there were no updates to mailmap. No reviews from Bhupesh, either,
so change the maintainer to Bjorn and Konrad (Qualcomm SoC maintainers).
Cc: Bhupesh Sharma <bhupesh.linux@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Konrad Dybcio <konradybcio@kernel.org>
Message-ID: <20241130094758.15553-1-krzysztof.kozlowski@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Document the crypto engine on the QCS8300 Platform.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add the compatible string for QCom ICE on qcs8300 SoCs.
Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Document QCS8300 compatible for the True Random Number
Generator.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The type definition of "fsl,liodn" is defined as uint32 in
crypto/fsl,sec-v4.0.yaml and uint32-array in soc/fsl/fsl,bman.yaml,
soc/fsl/fsl,qman-portal.yaml, and soc/fsl/fsl,qman.yaml. Unify the type to
be uint32-array and constraint the single entry cases.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241113225614.1782862-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Document the crypto engine on the SA8775P Platform.
Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Document SA8255p compatible for the True Random Number Generator.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add two description for register space of rtic. There are two register
space, one is for control and status, the other optional space is
recoverable error indication register space.
Fix below CHECK_DTBS error:
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dtb: crypto@1700000: rtic@60000:reg: [[393216, 256], [396800, 24]] is too long
from schema $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The Allwinner H616 has a crypto engine very similar to the one in the
H6, although all addresses in the DMA descriptors are shifted by 2 bits,
to accommodate for the larger physical address space. That makes it
incompatible to the H6 variant, and thus requires a new compatible
string. Clock wise it relies on the internal oscillator for the TRNG,
so needs all four possible clocks specified.
Add the compatible string to the list of recognised names, and add the
H616 to list of devices requiring all four clocks.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
API:
- Remove crypto stats interface.
Algorithms:
- Add faster AES-XTS on modern x86_64 CPUs.
- Forbid curves with order less than 224 bits in ecc (FIPS 186-5).
- Add ECDSA NIST P521.
Drivers:
- Expose otp zone in atmel.
- Add dh fallback for primes > 4K in qat.
- Add interface for live migration in qat.
- Use dma for aes requests in starfive.
- Add full DMA support for stm32mpx in stm32.
- Add Tegra Security Engine driver.
Others:
- Introduce scope-based x509_certificate allocation.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEn51F/lCuNhUwmDeSxycdCkmxi6cFAmZBjXMACgkQxycdCkmx
i6cQ7g/+JPKnzQedhpJSK5AnkAkqO9kJ16JdeB7AtdSeZZA/EIFxuXZ3Fv1fH44y
1CCibowc5zdss8F/1iOqPc57u5vy2Mjyw8qlhs7JlmcYf/lo7CBGfT8Uxo7BK/S9
n+/+y47Xu5p3yt/c6ldrwqjOaWaYuaCKICZtS91XVvrxM80iVnmDSQCNkcch4KQ4
nsdcVJhS4lOStBNjKtkhWlgufqdp8RPzKYH2B6GbW9z6en8WeTbnoMhgqjqQ3UID
/DHtixyee0MDUDReQrixyCM3XMV5er/qBMoDrCxipBuVrr4GMd2GlCEaZbXfTUW0
3K8Nle4KMMqi81lBAQKiD/hRjrC68FHOvVRGHtZntR0+NZ/nlinXCVWv4iHwRzAB
7BOqRTC3mfv+uMhTvgwQAkXCHAhivMokSzTaDCIrzPLjKIx2BOfVZKmPBt98LxeW
8/JfgEK4gX6wxe4GRftueEApCfWQrwYK60j5bIkescaJ/mI7M5bEByvTTob1lAka
Fw5kGDy8dVnrG9HagLwnXoI1pIGmca8hV1t24Vf1OCdWLgOW+GTCIuyutL2c9AWv
0vEbytGZl69XJlIgQGVcv9RM6NlIXxHwfSHU59N/SHTXhlHjm1XWi3HCiJaZ1b6+
pcILMJ29FMs8LobiN7PT+rNu6fboaH0/o+R7OK9mKRut864xFTk=
=NDS0
-----END PGP SIGNATURE-----
Merge tag 'v6.10-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto updates from Herbert Xu:
"API:
- Remove crypto stats interface
Algorithms:
- Add faster AES-XTS on modern x86_64 CPUs
- Forbid curves with order less than 224 bits in ecc (FIPS 186-5)
- Add ECDSA NIST P521
Drivers:
- Expose otp zone in atmel
- Add dh fallback for primes > 4K in qat
- Add interface for live migration in qat
- Use dma for aes requests in starfive
- Add full DMA support for stm32mpx in stm32
- Add Tegra Security Engine driver
Others:
- Introduce scope-based x509_certificate allocation"
* tag 'v6.10-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (123 commits)
crypto: atmel-sha204a - provide the otp content
crypto: atmel-sha204a - add reading from otp zone
crypto: atmel-i2c - rename read function
crypto: atmel-i2c - add missing arg description
crypto: iaa - Use kmemdup() instead of kzalloc() and memcpy()
crypto: sahara - use 'time_left' variable with wait_for_completion_timeout()
crypto: api - use 'time_left' variable with wait_for_completion_killable_timeout()
crypto: caam - i.MX8ULP donot have CAAM page0 access
crypto: caam - init-clk based on caam-page0-access
crypto: starfive - Use fallback for unaligned dma access
crypto: starfive - Do not free stack buffer
crypto: starfive - Skip unneeded fallback allocation
crypto: starfive - Skip dma setup for zeroed message
crypto: hisilicon/sec2 - fix for register offset
crypto: hisilicon/debugfs - mask the unnecessary info from the dump
crypto: qat - specify firmware files for 402xx
crypto: x86/aes-gcm - simplify GCM hash subkey derivation
crypto: x86/aes-gcm - delete unused GCM assembly code
crypto: x86/aes-xts - simplify loop in xts_crypt_slowpath()
hwrng: stm32 - repair clock handling
...
Add DT binding document for Tegra Security Engine.
The AES and HASH algorithms are handled independently by separate
engines within the Security Engine. These engines are registered
as two separate crypto engine drivers.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
access-controllers is an optional property that allows a peripheral to
refer to one or more domain access controller(s).
Description of this property is added to all peripheral binding files of
the peripheral under the STM32 firewall controller. It allows an accurate
representation of the hardware, where various peripherals are connected
to a firewall bus. The firewall can then check the peripheral accesses
before allowing its device to probe.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Document the compatible used for the inline crypto engine found on
SC7280.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add compatible string and additional interrupt for StarFive JH8100
crypto engine.
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Document the compatible used for the inline crypto engine found on
SC7180.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David Wronek <davidwronek@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
