2 Commits

Author	SHA1	Message	Date
Rohit Visavalia	b00b08a596	dt-bindings: clock: xilinx: Add reset GPIO for VCU ... It is marked as optional as some of the ZynqMP designs are having vcu_reset (reset pin of VCU IP) driven by proc_sys_reset, proc_sys_reset is another PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by axi_gpio or PS GPIO so there will be no GPIO entry. Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com> Link: https://lore.kernel.org/r/20250107044038.100945-3-rohit.visavalia@amd.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-01-07 11:48:23 -08:00
Rohit Visavalia	b51adc7755	dt-bindings: clock: xilinx: Convert VCU bindings to dtschema ... Convert AMD (Xilinx) VCU bindings to yaml format. Additional changes: - move xlnx_vcu DT binding to clock from soc following commit a2fe7baa27 ("clk: xilinx: move xlnx_vcu clock driver from soc") - corrected clock sequence as per xilinx device-tree generator Signed-off-by: Rohit Visavalia <rohit.visavalia@xilinx.com> Link: https://lore.kernel.org/r/20250107044038.100945-2-rohit.visavalia@amd.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-01-07 11:48:14 -08:00