2 Commits

Author	SHA1	Message	Date
Xingyu Wu	2110add84b	dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs ... Add PLL clock inputs from PLL clock generator. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>	2023-07-19 18:08:00 +01:00
Emil Renner Berthing	7fce1e39f0	dt-bindings: clock: Add StarFive JH7110 system clock and reset generator ... Add bindings for the system clock and reset generator (SYSCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>	2023-04-05 15:43:15 +01:00