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arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588

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Enabling the GPU power domain requires that the GPU regulator is
enabled. The regulator is enabled at boot time, but gets disabled
automatically when there are no users.

This means the system might run into a failure state hanging the
whole system for the following use cases:

 * if the GPU driver is being probed late (e.g. build as a
   module and firmware is not in initramfs), the regulator
   might already have been disabled. In that case the power
   domain is enabled before the regulator.
 * unbinding the GPU driver will disable the PM domain and
   the regulator. When the driver is bound again, the PM
   domain will be enabled before the regulator and error
   appears.

Avoid this by adding an explicit regulator dependency to the
power domain.

Tested-by: Heiko Stuebner <heiko@sntech.de>
Reported-by: Adrián Martínez Larumbe <adrian.larumbe@collabora.com>
Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Sebastian Reichel 2025-02-20 19:58:11 +01:00 committed by Heiko Stuebner
parent 254324dbe3
commit f94500eb73
30 changed files with 117 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi
View File

@ -114,6 +114,10 @@ regulator-state-mem {
};
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&saradc {
vref-supply = <&avcc_1v8_s0>;
status = "okay";

4
arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
View File

@ -318,6 +318,10 @@ &pcie3x4 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {

2
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
View File

@ -875,7 +875,7 @@ power-domain@RK3588_PD_NPU2 {
};
};
/* These power domains are grouped by VD_GPU */
power-domain@RK3588_PD_GPU {
pd_gpu: power-domain@RK3588_PD_GPU {
reg = <RK3588_PD_GPU>;
clocks = <&cru CLK_GPU>,
<&cru CLK_GPU_COREGROUP>,

4
arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi
View File

@ -277,6 +277,10 @@ &pcie2x1l2 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {

4
arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
View File

@ -126,6 +126,10 @@ regulator-state-mem {
};
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
leds {
led_user_en: led_user_en {

4
arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
View File

@ -550,6 +550,10 @@ &pcie3x4 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
audio {
hp_detect: headphone-detect {

4
arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi
View File

@ -205,6 +205,10 @@ regulator-state-mem {
};
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
leds {
led_rgb_b: led-rgb-b {

4
arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi
View File

@ -108,6 +108,10 @@ regulator-state-mem {
};
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&sdhci {
bus-width = <8>;
no-sdio;

4
arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi
View File

@ -256,6 +256,10 @@ &pcie2x1l2 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
gpio-leds {
led_sys_pin: led-sys-pin {

4
arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts
View File

@ -334,6 +334,10 @@ wifi: wifi@0,0 {
};
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {

4
arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
View File

@ -451,6 +451,10 @@ &pcie3x4 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
emmc {
emmc_reset: emmc-reset {

4
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
View File

@ -565,6 +565,10 @@ &pcie3x4 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
gpio-leds {
sys_led_pin: sys-led-pin {

4
arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
View File

@ -312,6 +312,10 @@ &pcie3x4 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
pcie2 {
pcie2_0_rst: pcie2-0-rst {

4
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi
View File

@ -348,6 +348,10 @@ &pcie3x4 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&saradc {
vref-supply = <&vcc_1v8_s0>;
status = "okay";

4
arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
View File

@ -347,6 +347,10 @@ rgmii_phy: ethernet-phy@1 {
};
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {

4
arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
View File

@ -598,6 +598,10 @@ &pcie3x4 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
hym8563 {
rtc_int: rtc-int {

4
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
View File

@ -425,6 +425,10 @@ &pcie3x4 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {

4
arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
View File

@ -335,6 +335,10 @@ &pcie3x4 {
reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>;
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
emmc {
emmc_reset: emmc-reset {

4
arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts
View File

@ -289,6 +289,10 @@ rgmii_phy: ethernet-phy@1 {
};
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
rtl8211f {
rtl8211f_rst: rtl8211f-rst {

4
arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
View File

@ -287,6 +287,10 @@ &pcie3x4 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
fan {
fan_int: fan-int {

4
arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts
View File

@ -361,6 +361,10 @@ &pcie2x1l2 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {

4
arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts
View File

@ -340,6 +340,10 @@ &pcie2x1l2 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
audio {
hp_detect: headphone-detect {

4
arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts
View File

@ -675,6 +675,10 @@ &pcie2x1l1 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
audio-amplifier {
headphone_amplifier_en: headphone-amplifier-en {

4
arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
View File

@ -455,6 +455,10 @@ &pcie2x1l2 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
bluetooth-pins {
bt_reset: bt-reset {

4
arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
View File

@ -233,6 +233,10 @@ hym8563: rtc@51 {
};
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
vdd_sd {
vdd_sd_en: vdd-sd-en {

4
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
View File

@ -359,6 +359,10 @@ &pcie2x1l2 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
gpio-key {
key1_pin: key1-pin {

4
arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts
View File

@ -433,6 +433,10 @@ &pcie2x1l2 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
lcd {
lcd_pwren: lcd-pwren {

4
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi
View File

@ -365,6 +365,10 @@ rgmii_phy1: ethernet-phy@1 {
};
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {

4
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
View File

@ -359,6 +359,10 @@ &pcie2x1l2 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
leds {
io_led: io-led {

4
arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
View File

@ -455,6 +455,10 @@ &pcie2x1l2 {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
leds {
led_pins: led-pins {