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arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100
Describe PCIe3 controller and PHY. Also add required system resources like regulators, clocks, interrupts and registers configuration for PCIe3. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241105073615.3076979-1-quic_qianyu@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Qiang Yu
Bjorn Andersson
parent
798515297c
commit
f8af195bee
@ -743,7 +743,7 @@ gcc: clock-controller@100000 {
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clocks = <&bi_tcxo_div2>,
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<&sleep_clk>,
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<0>,
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<&pcie3_phy>,
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<&pcie4_phy>,
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<&pcie5_phy>,
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<&pcie6a_phy>,
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@ -2906,6 +2906,208 @@ mmss_noc: interconnect@1780000 {
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#interconnect-cells = <2>;
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};
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pcie3: pcie@1bd0000 {
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device_type = "pci";
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compatible = "qcom,pcie-x1e80100";
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reg = <0x0 0x01bd0000 0x0 0x3000>,
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<0x0 0x78000000 0x0 0xf1d>,
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<0x0 0x78000f40 0x0 0xa8>,
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<0x0 0x78001000 0x0 0x1000>,
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<0x0 0x78100000 0x0 0x100000>,
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<0x0 0x01bd3000 0x0 0x1000>;
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reg-names = "parf",
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"dbi",
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"elbi",
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"atu",
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"config",
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"mhi";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>,
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<0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>,
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<0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
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bus-range = <0x00 0xff>;
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dma-coherent;
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linux,pci-domain = <3>;
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num-lanes = <8>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7",
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"global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
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<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_3_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
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<&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a",
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"noc_aggr",
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"cnoc_sf_axi";
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assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "pcie-mem",
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"cpu-pcie";
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resets = <&gcc GCC_PCIE_3_BCR>,
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<&gcc GCC_PCIE_3_LINK_DOWN_BCR>;
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reset-names = "pci",
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"link_down";
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power-domains = <&gcc GCC_PCIE_3_GDSC>;
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phys = <&pcie3_phy>;
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phy-names = "pciephy";
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operating-points-v2 = <&pcie3_opp_table>;
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status = "disabled";
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pcie3_opp_table: opp-table {
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compatible = "operating-points-v2";
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/* GEN 1 x1 */
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opp-2500000 {
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opp-hz = /bits/ 64 <2500000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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opp-peak-kBps = <250000 1>;
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};
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/* GEN 1 x2 and GEN 2 x1 */
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opp-5000000 {
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opp-hz = /bits/ 64 <5000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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opp-peak-kBps = <500000 1>;
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};
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/* GEN 1 x4 and GEN 2 x2 */
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opp-10000000 {
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opp-hz = /bits/ 64 <10000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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opp-peak-kBps = <1000000 1>;
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};
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/* GEN 1 x8 and GEN 2 x4 */
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opp-20000000 {
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opp-hz = /bits/ 64 <20000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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opp-peak-kBps = <2000000 1>;
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};
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/* GEN 2 x8 */
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opp-40000000 {
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opp-hz = /bits/ 64 <40000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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opp-peak-kBps = <4000000 1>;
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};
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/* GEN 3 x1 */
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opp-8000000 {
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opp-hz = /bits/ 64 <8000000>;
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required-opps = <&rpmhpd_opp_svs>;
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opp-peak-kBps = <984500 1>;
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};
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/* GEN 3 x2 and GEN 4 x1 */
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opp-16000000 {
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opp-hz = /bits/ 64 <16000000>;
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required-opps = <&rpmhpd_opp_svs>;
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opp-peak-kBps = <1969000 1>;
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};
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/* GEN 3 x4 and GEN 4 x2 */
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opp-32000000 {
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opp-hz = /bits/ 64 <32000000>;
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required-opps = <&rpmhpd_opp_svs>;
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opp-peak-kBps = <3938000 1>;
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};
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/* GEN 3 x8 and GEN 4 x4 */
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opp-64000000 {
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opp-hz = /bits/ 64 <64000000>;
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required-opps = <&rpmhpd_opp_svs>;
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opp-peak-kBps = <7876000 1>;
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};
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/* GEN 4 x8 */
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opp-128000000 {
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opp-hz = /bits/ 64 <128000000>;
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required-opps = <&rpmhpd_opp_svs>;
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opp-peak-kBps = <15753000 1>;
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};
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};
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};
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pcie3_phy: phy@1be0000 {
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compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
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reg = <0 0x01be0000 0 0x10000>;
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clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
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<&tcsr TCSR_PCIE_8L_CLKREF_EN>,
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<&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_3_PIPE_CLK>,
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<&gcc GCC_PCIE_3_PIPEDIV2_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"rchng",
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"pipe",
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"pipediv2";
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resets = <&gcc GCC_PCIE_3_PHY_BCR>,
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<&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>;
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reset-names = "phy",
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"phy_nocsr";
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assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
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assigned-clock-rates = <100000000>;
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power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
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#clock-cells = <0>;
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clock-output-names = "pcie3_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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pcie6a: pci@1bf8000 {
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device_type = "pci";
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compatible = "qcom,pcie-x1e80100";
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