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arm64: dts: mt8173: Add clock controller device nodes

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This adds the device nodes providing clocks on the Mediatek MT8173.
These are: topckgen, infracfg, pericfg and apmixedsys. These are
fed by two oscillators also added by this patch.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Sascha Hauer 2015-05-20 15:32:44 +02:00 committed by Matthias Brugger
parent d770e558e2
commit f2ce701495
1 changed files with 47 additions and 5 deletions
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52
arch/arm64/boot/dts/mediatek/mt8173.dtsi
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@ -11,6 +11,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include "mt8173-pinfunc.h" #include "mt8173-pinfunc.h"
@ -87,6 +88,20 @@ uart_clk: dummy26m {
#clock-cells = <0>; #clock-cells = <0>;
}; };
clk26m: oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
clk32k: oscillator@1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-output-names = "clk32k";
};
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
@ -106,11 +121,32 @@ soc {
compatible = "simple-bus"; compatible = "simple-bus";
ranges; ranges;
/* topckgen: clock-controller@10000000 {
* Pinctrl access register at 0x10005000 through regmap. compatible = "mediatek,mt8173-topckgen";
* Register 0x1000b000 is used by EINT. reg = <0 0x10000000 0 0x1000>;
*/ #clock-cells = <1>;
pio: pinctrl@10005000 { };
infracfg: power-controller@10001000 {
compatible = "mediatek,mt8173-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pericfg: power-controller@10003000 {
compatible = "mediatek,mt8173-pericfg", "syscon";
reg = <0 0x10003000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
syscfg_pctl_a: syscfg_pctl_a@10005000 {
compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
pio: pinctrl@0x10005000 {
compatible = "mediatek,mt8173-pinctrl"; compatible = "mediatek,mt8173-pinctrl";
reg = <0 0x1000b000 0 0x1000>; reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>; mediatek,pctl-regmap = <&syscfg_pctl_a>;
@ -138,6 +174,12 @@ sysirq: intpol-controller@10200620 {
reg = <0 0x10200620 0 0x20>; reg = <0 0x10200620 0 0x20>;
}; };
apmixedsys: clock-controller@10209000 {
compatible = "mediatek,mt8173-apmixedsys";
reg = <0 0x10209000 0 0x1000>;
#clock-cells = <1>;
};
gic: interrupt-controller@10220000 { gic: interrupt-controller@10220000 {
compatible = "arm,gic-400"; compatible = "arm,gic-400";
#interrupt-cells = <3>; #interrupt-cells = <3>;