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arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable GBETH

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Enable GBETH nodes on RZ/V2N EVK.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250514101528.41663-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2025-05-14 11:15:20 +01:00 committed by Geert Uytterhoeven
parent c8c8a57c5b
commit f111192baa
1 changed files with 66 additions and 0 deletions
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66
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
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@ -15,6 +15,8 @@ / {
compatible = "renesas,rzv2n-evk", "renesas,r9a09g056n48", "renesas,r9a09g056"; compatible = "renesas,rzv2n-evk", "renesas,r9a09g056n48", "renesas,r9a09g056";
aliases { aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
mmc1 = &sdhi1; mmc1 = &sdhi1;
serial0 = &scif; serial0 = &scif;
}; };
@ -54,7 +56,71 @@ &audio_extal_clk {
clock-frequency = <22579200>; clock-frequency = <22579200>;
}; };
&eth0 {
pinctrl-0 = <&eth0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
};
&eth1 {
pinctrl-0 = <&eth1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
};
&mdio0 {
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
reg = <0>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
&mdio1 {
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
reg = <0>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
&pinctrl { &pinctrl {
eth0_pins: eth0 {
pins = "ET0_TXC_TXCLK";
output-enable;
};
eth1_pins: eth0 {
pins = "ET1_TXC_TXCLK";
output-enable;
};
scif_pins: scif { scif_pins: scif {
pins = "SCIF_TXD", "SCIF_RXD"; pins = "SCIF_TXD", "SCIF_RXD";
renesas,output-impedance = <1>; renesas,output-impedance = <1>;