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arm64: dts: qcom: Add X1P42100 SoC and CRD

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The X1 family is split into two parts: the 10- and 12-core parts are
variants of the same silicon with different fusing, whereas the 8-core
ones are a separate design. Thankfully, the software interface is only
barely different, letting us reuse much of the existing X1 work.

Introduce support for the X1P42100 SoC and the CRD based on it, through
overlaying some bits. Everything we already support on X1E80100 and
friends, minus the GPU, should work as-is.

Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-6-72cd4cdc767b@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Konrad Dybcio 2025-02-03 15:43:25 +01:00 committed by Bjorn Andersson
parent fbf5e00758
commit f08edb5299
5 changed files with 115 additions and 16 deletions
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1
arch/arm64/boot/dts/qcom/Makefile
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@ -298,3 +298,4 @@ dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb

2
arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi
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@ -110,7 +110,7 @@ trip1 {
};
};
pmc8380-6-thermal {
pmc8380_6_thermal: pmc8380-6-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmc8380_6_temp_alarm>;

30
arch/arm64/boot/dts/qcom/x1e80100.dtsi
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@ -252,7 +252,7 @@ core3 {
};
};
cluster2 {
cpu_map_cluster2: cluster2 {
core0 {
cpu = <&cpu8>;
};
@ -8212,7 +8212,7 @@ opp-9 {
};
/* cluster0 */
pmu@240b3400 {
bwmon_cluster0: pmu@240b3400 {
compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0 0x240b3400 0 0x600>;
@ -8222,6 +8222,19 @@ pmu@240b3400 {
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&cpu_bwmon_opp_table>;
};
/* cluster2 */
bwmon_cluster2: pmu@240b5400 {
compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0 0x240b5400 0 0x600>;
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&cpu_bwmon_opp_table>;
cpu_bwmon_opp_table: opp-table {
compatible = "operating-points-v2";
@ -8252,19 +8265,6 @@ opp-5 {
};
};
/* cluster2 */
pmu@240b5400 {
compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0 0x240b5400 0 0x600>;
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&cpu_bwmon_opp_table>;
};
/* cluster1 */
pmu@240b6400 {
compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";

17
arch/arm64/boot/dts/qcom/x1p42100-crd.dts Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "x1p42100.dtsi"
#include "x1-crd.dtsi"
/delete-node/ &pmc8380_6;
/delete-node/ &pmc8380_6_thermal;
/ {
model = "Qualcomm Technologies, Inc. X1P42100 CRD";
compatible = "qcom,x1p42100-crd", "qcom,x1p42100";
};

81
arch/arm64/boot/dts/qcom/x1p42100.dtsi Normal file
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@ -0,0 +1,81 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* X1P42100 is heavily based on X1E80100, with some meaningful differences */
#include "x1e80100.dtsi"
/delete-node/ &bwmon_cluster0;
/delete-node/ &cluster_pd2;
/delete-node/ &cpu_map_cluster2;
/delete-node/ &cpu8;
/delete-node/ &cpu9;
/delete-node/ &cpu10;
/delete-node/ &cpu11;
/delete-node/ &cpu_pd8;
/delete-node/ &cpu_pd9;
/delete-node/ &cpu_pd10;
/delete-node/ &cpu_pd11;
/delete-node/ &pcie3_phy;
&gcc {
compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
};
/* The GPU is physically different and will be brought up later */
&gpu {
/delete-property/ compatible;
};
&gpucc {
compatible = "qcom,x1p42100-gpucc";
};
/* PCIe3 has half the lanes compared to X1E80100 */
&pcie3 {
num-lanes = <4>;
};
&pcie6a_phy {
compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy";
};
&soc {
/* The PCIe3 PHY on X1P42100 uses a different IP block */
pcie3_phy: phy@1bd4000 {
compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy";
reg = <0x0 0x01bd4000 0x0 0x2000>,
<0x0 0x01bd6000 0x0 0x2000>;
clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
<&tcsr TCSR_PCIE_8L_CLKREF_EN>,
<&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_3_PIPE_CLK>,
<&gcc GCC_PCIE_3_PIPEDIV2_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"rchng",
"pipe",
"pipediv2";
resets = <&gcc GCC_PCIE_3_PHY_BCR>,
<&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>;
reset-names = "phy",
"phy_nocsr";
assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
#clock-cells = <0>;
clock-output-names = "pcie3_pipe_clk";
#phy-cells = <0>;
status = "disabled";
};
};