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arm64: dts: mt8195: Add pcie and pcie phy nodes

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Add pcie and pcie phy nodes for mt8195.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221103025656.8714-3-tinghan.shen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Tinghan Shen 2022-11-03 10:56:55 +08:00 committed by Matthias Brugger
parent 07ce611c70
commit ecc0af6a3f
1 changed files with 150 additions and 0 deletions
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150
arch/arm64/boot/dts/mediatek/mt8195.dtsi
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@ -13,6 +13,7 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/power/mt8195-power.h>
#include <dt-bindings/reset/mt8195-resets.h>
/ {
compatible = "mediatek,mt8195";
@ -1185,6 +1186,110 @@ xhci3: usb@112b0000 {
status = "disabled";
};
pcie0: pcie@112f0000 {
compatible = "mediatek,mt8195-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x112f0000 0 0x4000>;
reg-names = "pcie-mac";
interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x20000000
0x0 0x20000000 0 0x200000>,
<0x82000000 0 0x20200000
0x0 0x20200000 0 0x3e00000>;
iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
iommu-map-mask = <0x0>;
clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
<&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
<&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
clock-names = "pl_250m", "tl_26m", "tl_96m",
"tl_32k", "peri_26m", "peri_mem";
assigned-clocks = <&topckgen CLK_TOP_TL>;
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
phys = <&pciephy>;
phy-names = "pcie-phy";
power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
reset-names = "mac";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
status = "disabled";
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie1: pcie@112f8000 {
compatible = "mediatek,mt8195-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x112f8000 0 0x4000>;
reg-names = "pcie-mac";
interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x24000000
0x0 0x24000000 0 0x200000>,
<0x82000000 0 0x24200000
0x0 0x24200000 0 0x3e00000>;
iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
iommu-map-mask = <0x0>;
clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
<&clk26m>,
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
<&clk26m>,
<&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
/* Designer has connect pcie1 with peri_mem_p0 clock */
<&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
clock-names = "pl_250m", "tl_26m", "tl_96m",
"tl_32k", "peri_26m", "peri_mem";
assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
phys = <&u3port1 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
reset-names = "mac";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
status = "disabled";
pcie_intc1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
nor_flash: spi@1132c000 {
compatible = "mediatek,mt8195-nor",
"mediatek,mt8173-nor";
@ -1244,6 +1349,34 @@ u2_intr_p3: usb2-intr-p3@189,2 {
reg = <0x189 0x2>;
bits = <7 5>;
};
pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
reg = <0x190 0x1>;
bits = <0 4>;
};
pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
reg = <0x190 0x1>;
bits = <4 4>;
};
pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
reg = <0x191 0x1>;
bits = <0 4>;
};
pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
reg = <0x191 0x1>;
bits = <4 4>;
};
pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
reg = <0x192 0x1>;
bits = <0 4>;
};
pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
reg = <0x192 0x1>;
bits = <4 4>;
};
pciephy_glb_intr: pciephy-glb-intr@193 {
reg = <0x193 0x1>;
bits = <0 4>;
};
};
u3phy2: t-phy@11c40000 {
@ -1464,6 +1597,23 @@ u3port0: usb-phy@700 {
};
};
pciephy: phy@11e80000 {
compatible = "mediatek,mt8195-pcie-phy";
reg = <0 0x11e80000 0 0x10000>;
reg-names = "sif";
nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
<&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>,
<&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>,
<&pciephy_rx_ln1>;
nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
"tx_ln0_nmos", "rx_ln0",
"tx_ln1_pmos", "tx_ln1_nmos",
"rx_ln1";
power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
#phy-cells = <0>;
status = "disabled";
};
ufsphy: ufs-phy@11fa0000 {
compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
reg = <0 0x11fa0000 0 0xc000>;