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drm/amdgpu/vcn2.5: split code along instances

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Split the code on a per instance basis.  This will allow
us to use the per instance functions in the future to
handle more things per instance.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2024-11-13 11:51:12 -05:00
parent 53472eeb22
commit ebc25499de
1 changed files with 402 additions and 421 deletions
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93
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
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@ -452,18 +452,17 @@ static int vcn_v2_5_resume(struct amdgpu_ip_block *ip_block)
* vcn_v2_5_mc_resume - memory controller programming * vcn_v2_5_mc_resume - memory controller programming
* *
* @adev: amdgpu_device pointer * @adev: amdgpu_device pointer
* @i: instance to resume
* *
* Let the VCN memory controller know it's offsets * Let the VCN memory controller know it's offsets
*/ */
static void vcn_v2_5_mc_resume(struct amdgpu_device *adev) static void vcn_v2_5_mc_resume(struct amdgpu_device *adev, int i)
{ {
uint32_t size; uint32_t size;
uint32_t offset; uint32_t offset;
int i;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i)) if (adev->vcn.harvest_config & (1 << i))
continue; return;
size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
/* cache window 0: fw */ /* cache window 0: fw */
@ -510,7 +509,6 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0, WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0,
AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
} }
}
static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
{ {
@ -612,17 +610,16 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
* vcn_v2_5_disable_clock_gating - disable VCN clock gating * vcn_v2_5_disable_clock_gating - disable VCN clock gating
* *
* @adev: amdgpu_device pointer * @adev: amdgpu_device pointer
* @i: instance to disable clockgating on
* *
* Disable clock gating for VCN block * Disable clock gating for VCN block
*/ */
static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev) static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev, int i)
{ {
uint32_t data; uint32_t data;
int i;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i)) if (adev->vcn.harvest_config & (1 << i))
continue; return;
/* UVD disable CGC */ /* UVD disable CGC */
data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
@ -723,7 +720,6 @@ static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
} }
}
static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev, static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
uint8_t sram_sel, int inst_idx, uint8_t indirect) uint8_t sram_sel, int inst_idx, uint8_t indirect)
@ -774,20 +770,19 @@ static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
} }
/** /**
* vcn_v2_5_enable_clock_gating - enable VCN clock gating * vcn_v2_5_enable_clock_gating_inst - enable VCN clock gating
* *
* @adev: amdgpu_device pointer * @adev: amdgpu_device pointer
* @i: instance to enable clockgating on
* *
* Enable clock gating for VCN block * Enable clock gating for VCN block
*/ */
static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev) static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev, int i)
{ {
uint32_t data = 0; uint32_t data = 0;
int i;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i)) if (adev->vcn.harvest_config & (1 << i))
continue; return;
/* enable UVD CGC */ /* enable UVD CGC */
data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
@ -833,7 +828,6 @@ static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
} }
}
static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx, static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx,
bool indirect) bool indirect)
@ -1006,24 +1000,22 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
return 0; return 0;
} }
static int vcn_v2_5_start(struct amdgpu_device *adev) static int vcn_v2_5_start(struct amdgpu_device *adev, int i)
{ {
volatile struct amdgpu_fw_shared *fw_shared =
adev->vcn.inst[i].fw_shared.cpu_addr;
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
uint32_t rb_bufsz, tmp; uint32_t rb_bufsz, tmp;
int i, j, k, r; int j, k, r;
if (adev->vcn.harvest_config & (1 << i))
return 0;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->pm.dpm_enabled) if (adev->pm.dpm_enabled)
amdgpu_dpm_enable_vcn(adev, true, i); amdgpu_dpm_enable_vcn(adev, true, i);
}
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
if (adev->vcn.harvest_config & (1 << i)) return vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
continue;
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
continue;
}
/* disable register anti-hang mechanism */ /* disable register anti-hang mechanism */
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,
@ -1032,17 +1024,13 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
/* set uvd status busy */ /* set uvd status busy */
tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
}
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
return 0; return 0;
/* SW clock gating */ /* SW clock gating */
vcn_v2_5_disable_clock_gating(adev); vcn_v2_5_disable_clock_gating(adev, i);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
/* enable VCPU clock */ /* enable VCPU clock */
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
@ -1085,14 +1073,9 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
}
vcn_v2_5_mc_resume(adev); vcn_v2_5_mc_resume(adev, i);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
if (adev->vcn.harvest_config & (1 << i))
continue;
/* VCN global tiling registers */ /* VCN global tiling registers */
WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,
adev->gfx.config.gb_addr_config); adev->gfx.config.gb_addr_config);
@ -1196,7 +1179,6 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
}
return 0; return 0;
} }
@ -1425,18 +1407,15 @@ static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
return 0; return 0;
} }
static int vcn_v2_5_stop(struct amdgpu_device *adev) static int vcn_v2_5_stop(struct amdgpu_device *adev, int i)
{ {
uint32_t tmp; uint32_t tmp;
int i, r = 0; int r;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i)) if (adev->vcn.harvest_config & (1 << i))
continue; return 0;
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
r = vcn_v2_5_stop_dpg_mode(adev, i); return vcn_v2_5_stop_dpg_mode(adev, i);
continue;
}
/* wait for vcn idle */ /* wait for vcn idle */
r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
@ -1479,18 +1458,15 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
/* clear status */ /* clear status */
WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
vcn_v2_5_enable_clock_gating(adev); vcn_v2_5_enable_clock_gating(adev, i);
/* enable register anti-hang mechanism */ /* enable register anti-hang mechanism */
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
}
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->pm.dpm_enabled) if (adev->pm.dpm_enabled)
amdgpu_dpm_enable_vcn(adev, false, i); amdgpu_dpm_enable_vcn(adev, false, i);
}
return 0; return 0;
} }
@ -1811,16 +1787,19 @@ static int vcn_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
{ {
struct amdgpu_device *adev = ip_block->adev; struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE); bool enable = (state == AMD_CG_STATE_GATE);
int i;
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
return 0; return 0;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (enable) { if (enable) {
if (!vcn_v2_5_is_idle(adev)) if (!vcn_v2_5_is_idle(adev))
return -EBUSY; return -EBUSY;
vcn_v2_5_enable_clock_gating(adev); vcn_v2_5_enable_clock_gating(adev, i);
} else { } else {
vcn_v2_5_disable_clock_gating(adev); vcn_v2_5_disable_clock_gating(adev, i);
}
} }
return 0; return 0;
@ -1830,7 +1809,7 @@ static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state) enum amd_powergating_state state)
{ {
struct amdgpu_device *adev = ip_block->adev; struct amdgpu_device *adev = ip_block->adev;
int ret; int ret = 0, i;
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
return 0; return 0;
@ -1838,10 +1817,12 @@ static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
if (state == adev->vcn.cur_state) if (state == adev->vcn.cur_state)
return 0; return 0;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (state == AMD_PG_STATE_GATE) if (state == AMD_PG_STATE_GATE)
ret = vcn_v2_5_stop(adev); ret |= vcn_v2_5_stop(adev, i);
else else
ret = vcn_v2_5_start(adev); ret |= vcn_v2_5_start(adev, i);
}
if (!ret) if (!ret)
adev->vcn.cur_state = state; adev->vcn.cur_state = state;