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arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc

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The PCIe Gen4x2 PHY found in the SM8450 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.

Now the pcie1_phy exposes 2 clocks, properly add the pcie1_phy provided
clocks to the Global Clock Controller (GCC) node clocks inputs.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-1-10c650cfeade@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Neil Armstrong 2024-05-02 10:00:36 +02:00 committed by Bjorn Andersson
parent 7c0922fc89
commit e768628406
1 changed files with 4 additions and 4 deletions
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8
arch/arm64/boot/dts/qcom/sm8450.dtsi
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@ -754,8 +754,8 @@ gcc: clock-controller@100000 {
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&pcie0_phy>,
<&pcie1_phy>,
<0>,
<&pcie1_phy QMP_PCIE_PIPE_CLK>,
<&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
@ -2000,8 +2000,8 @@ pcie1_phy: phy@1c0e000 {
"rchng",
"pipe";
clock-output-names = "pcie_1_pipe_clk";
#clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk", "pcie_1_phy_aux_clk";
#clock-cells = <1>;
#phy-cells = <0>;