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PCI: j721e: Add TI J784S4 PCIe configuration

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Add PCIe configuration for J784S4 SoC platform which has 4x lane
support.

Link: https://lore.kernel.org/linux-pci/20231128054402.2155183-6-s-vadapalli@ti.com
Tested-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
This commit is contained in:
Matt Ranostay 2023-11-28 11:14:02 +05:30 committed by Krzysztof Wilczyński
parent 4490f559f7
commit e49ad66781
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GPG Key ID: 7C64768D3DE334E7
1 changed files with 22 additions and 0 deletions
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22
drivers/pci/controller/cadence/pci-j721e.c
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@ -330,6 +330,20 @@ static const struct j721e_pcie_data am64_pcie_ep_data = {
.max_lanes = 1, .max_lanes = 1,
}; };
static const struct j721e_pcie_data j784s4_pcie_rc_data = {
.mode = PCI_MODE_RC,
.quirk_retrain_flag = true,
.byte_access_allowed = false,
.linkdown_irq_regfield = LINK_DOWN,
.max_lanes = 4,
};
static const struct j721e_pcie_data j784s4_pcie_ep_data = {
.mode = PCI_MODE_EP,
.linkdown_irq_regfield = LINK_DOWN,
.max_lanes = 4,
};
static const struct of_device_id of_j721e_pcie_match[] = { static const struct of_device_id of_j721e_pcie_match[] = {
{ {
.compatible = "ti,j721e-pcie-host", .compatible = "ti,j721e-pcie-host",
@ -355,6 +369,14 @@ static const struct of_device_id of_j721e_pcie_match[] = {
.compatible = "ti,am64-pcie-ep", .compatible = "ti,am64-pcie-ep",
.data = &am64_pcie_ep_data, .data = &am64_pcie_ep_data,
}, },
{
.compatible = "ti,j784s4-pcie-host",
.data = &j784s4_pcie_rc_data,
},
{
.compatible = "ti,j784s4-pcie-ep",
.data = &j784s4_pcie_ep_data,
},
{}, {},
}; };