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arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices

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This patch define OOP tables for all CPUs.
This allows CPUFreq to function.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Takeshi Kihara 2019-01-15 21:02:42 +09:00 committed by Simon Horman
parent e536d27e92
commit dd7188eb4e
1 changed files with 25 additions and 0 deletions
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25
arch/arm64/boot/dts/renesas/r8a77990.dtsi
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@ -55,6 +55,27 @@ can_clk: can {
clock-frequency = <0>; clock-frequency = <0>;
}; };
cluster1_opp: opp_table10 {
compatible = "operating-points-v2";
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -66,6 +87,8 @@ a53_0: cpu@0 {
power-domains = <&sysc R8A77990_PD_CA53_CPU0>; power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>; next-level-cache = <&L2_CA53>;
enable-method = "psci"; enable-method = "psci";
clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
}; };
a53_1: cpu@1 { a53_1: cpu@1 {
@ -75,6 +98,8 @@ a53_1: cpu@1 {
power-domains = <&sysc R8A77990_PD_CA53_CPU1>; power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>; next-level-cache = <&L2_CA53>;
enable-method = "psci"; enable-method = "psci";
clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
}; };
L2_CA53: cache-controller-0 { L2_CA53: cache-controller-0 {