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arm64: mm: Wire up TCR.DS bit to PTE shareability fields

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When LPA2 is enabled, bits 8 and 9 of page and block descriptors become
part of the output address instead of carrying shareability attributes
for the region in question.

So avoid setting these bits if TCR.DS == 1, which means LPA2 is enabled.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20240214122845.2033971-74-ardb+git@google.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Ard Biesheuvel 2024-02-14 13:29:15 +01:00 committed by Catalin Marinas
parent 7ac8d5b242
commit db95ea787b
5 changed files with 25 additions and 2 deletions
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4
arch/arm64/Kconfig
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@ -1377,6 +1377,10 @@ config ARM64_PA_BITS
default 48 if ARM64_PA_BITS_48 default 48 if ARM64_PA_BITS_48
default 52 if ARM64_PA_BITS_52 default 52 if ARM64_PA_BITS_52
config ARM64_LPA2
def_bool y
depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES
choice choice
prompt "Endianness" prompt "Endianness"
default CPU_LITTLE_ENDIAN default CPU_LITTLE_ENDIAN

1
arch/arm64/include/asm/pgtable-hwdef.h
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@ -284,6 +284,7 @@
#define TCR_E0PD1 (UL(1) << 56) #define TCR_E0PD1 (UL(1) << 56)
#define TCR_TCMA0 (UL(1) << 57) #define TCR_TCMA0 (UL(1) << 57)
#define TCR_TCMA1 (UL(1) << 58) #define TCR_TCMA1 (UL(1) << 58)
#define TCR_DS (UL(1) << 59)
/* /*
* TTBR. * TTBR.

16
arch/arm64/include/asm/pgtable-prot.h
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@ -30,8 +30,8 @@
#define _PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) #define _PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
#define _PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) #define _PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
#define PROT_DEFAULT (_PROT_DEFAULT | PTE_MAYBE_NG) #define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_MAYBE_NG | PTE_MAYBE_SHARED | PTE_AF)
#define PROT_SECT_DEFAULT (_PROT_SECT_DEFAULT | PMD_MAYBE_NG) #define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_MAYBE_NG | PMD_MAYBE_SHARED | PMD_SECT_AF)
#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE)) #define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE)) #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
@ -67,7 +67,19 @@ extern bool arm64_use_ng_mappings;
#define PTE_MAYBE_NG (arm64_use_ng_mappings ? PTE_NG : 0) #define PTE_MAYBE_NG (arm64_use_ng_mappings ? PTE_NG : 0)
#define PMD_MAYBE_NG (arm64_use_ng_mappings ? PMD_SECT_NG : 0) #define PMD_MAYBE_NG (arm64_use_ng_mappings ? PMD_SECT_NG : 0)
#ifndef CONFIG_ARM64_LPA2
#define lpa2_is_enabled() false #define lpa2_is_enabled() false
#define PTE_MAYBE_SHARED PTE_SHARED
#define PMD_MAYBE_SHARED PMD_SECT_S
#else
static inline bool __pure lpa2_is_enabled(void)
{
return read_tcr() & TCR_DS;
}
#define PTE_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PTE_SHARED)
#define PMD_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PMD_SECT_S)
#endif
/* /*
* If we have userspace only BTI we don't want to mark kernel pages * If we have userspace only BTI we don't want to mark kernel pages

4
arch/arm64/mm/mmap.c
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@ -73,6 +73,10 @@ static int __init adjust_protection_map(void)
protection_map[VM_EXEC | VM_SHARED] = PAGE_EXECONLY; protection_map[VM_EXEC | VM_SHARED] = PAGE_EXECONLY;
} }
if (lpa2_is_enabled())
for (int i = 0; i < ARRAY_SIZE(protection_map); i++)
pgprot_val(protection_map[i]) &= ~PTE_SHARED;
return 0; return 0;
} }
arch_initcall(adjust_protection_map); arch_initcall(adjust_protection_map);

2
arch/arm64/mm/proc.S
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@ -466,6 +466,7 @@ alternative_else_nop_endif
*/ */
#define PTE_MAYBE_NG 0 #define PTE_MAYBE_NG 0
#define PTE_MAYBE_SHARED 0
mov_q x0, PIE_E0 mov_q x0, PIE_E0
msr REG_PIRE0_EL1, x0 msr REG_PIRE0_EL1, x0
@ -473,6 +474,7 @@ alternative_else_nop_endif
msr REG_PIR_EL1, x0 msr REG_PIR_EL1, x0
#undef PTE_MAYBE_NG #undef PTE_MAYBE_NG
#undef PTE_MAYBE_SHARED
mov x0, TCR2_EL1x_PIE mov x0, TCR2_EL1x_PIE
msr REG_TCR2_EL1, x0 msr REG_TCR2_EL1, x0