mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 06:39:05 +00:00
riscv: dts: add initial SpacemiT K1 SoC device tree
Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
Key features:
- 4 cores per cluster, 2 clusters on chip
- UART IP is Intel XScale UART
Some key considerations:
- ISA string is inferred from vendor documentation[2]
- Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
- No coherent DMA on this board
Inferred by taking vendor ethernet and MMC drivers to the mainline
kernel. Without dma-noncoherent in soc node, the driver fails.
- Add cache nodes
K1 SoC has 128 sets of 32KiB L1 I/D Cache for each hart, and 512 sets
of 512KiB L2 Cache for each cluster.
Currently only support booting into console with only uart, other
features will be added soon later.
Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Jesse Taube <jesse@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
This commit is contained in:
Yangyu Chen
Yixun Lan
parent
8814aa123a
commit
d8fe646919
459
arch/riscv/boot/dts/spacemit/k1.dtsi
Normal file
459
arch/riscv/boot/dts/spacemit/k1.dtsi
Normal file
@ -0,0 +1,459 @@
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "SpacemiT K1";
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compatible = "spacemit,k1";
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aliases {
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serial0 = &uart0;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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serial6 = &uart7;
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serial7 = &uart8;
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serial8 = &uart9;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <24000000>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu_0>;
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};
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core1 {
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cpu = <&cpu_1>;
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};
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core2 {
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cpu = <&cpu_2>;
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};
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core3 {
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cpu = <&cpu_3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu_4>;
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};
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core1 {
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cpu = <&cpu_5>;
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};
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core2 {
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cpu = <&cpu_6>;
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};
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core3 {
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cpu = <&cpu_7>;
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};
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};
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};
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cpu_0: cpu@0 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <0>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster0_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_1: cpu@1 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <1>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster0_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu1_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_2: cpu@2 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <2>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster0_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu2_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_3: cpu@3 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <3>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster0_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu3_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_4: cpu@4 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <4>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster1_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu4_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_5: cpu@5 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <5>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster1_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu5_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_6: cpu@6 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <6>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster1_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu6_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_7: cpu@7 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <7>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
|
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
|
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
|
||||
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
|
||||
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
|
||||
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
|
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riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-sets = <128>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&cluster1_l2_cache>;
|
||||
mmu-type = "riscv,sv39";
|
||||
|
||||
cpu7_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
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#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster0_l2_cache: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-block-size = <64>;
|
||||
cache-level = <2>;
|
||||
cache-size = <524288>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
};
|
||||
|
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cluster1_l2_cache: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-block-size = <64>;
|
||||
cache-level = <2>;
|
||||
cache-size = <524288>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
|
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soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&plic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dma-noncoherent;
|
||||
ranges;
|
||||
|
||||
uart0: serial@d4017000 {
|
||||
compatible = "spacemit,k1-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017000 0x0 0x100>;
|
||||
interrupts = <42>;
|
||||
clock-frequency = <14857000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@d4017100 {
|
||||
compatible = "spacemit,k1-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017100 0x0 0x100>;
|
||||
interrupts = <44>;
|
||||
clock-frequency = <14857000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@d4017200 {
|
||||
compatible = "spacemit,k1-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017200 0x0 0x100>;
|
||||
interrupts = <45>;
|
||||
clock-frequency = <14857000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@d4017300 {
|
||||
compatible = "spacemit,k1-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017300 0x0 0x100>;
|
||||
interrupts = <46>;
|
||||
clock-frequency = <14857000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@d4017400 {
|
||||
compatible = "spacemit,k1-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017400 0x0 0x100>;
|
||||
interrupts = <47>;
|
||||
clock-frequency = <14857000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@d4017500 {
|
||||
compatible = "spacemit,k1-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017500 0x0 0x100>;
|
||||
interrupts = <48>;
|
||||
clock-frequency = <14857000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart7: serial@d4017600 {
|
||||
compatible = "spacemit,k1-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017600 0x0 0x100>;
|
||||
interrupts = <49>;
|
||||
clock-frequency = <14857000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart8: serial@d4017700 {
|
||||
compatible = "spacemit,k1-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017700 0x0 0x100>;
|
||||
interrupts = <50>;
|
||||
clock-frequency = <14857000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart9: serial@d4017800 {
|
||||
compatible = "spacemit,k1-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017800 0x0 0x100>;
|
||||
interrupts = <51>;
|
||||
clock-frequency = <14857000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
plic: interrupt-controller@e0000000 {
|
||||
compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
|
||||
reg = <0x0 0xe0000000 0x0 0x4000000>;
|
||||
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
|
||||
<&cpu1_intc 11>, <&cpu1_intc 9>,
|
||||
<&cpu2_intc 11>, <&cpu2_intc 9>,
|
||||
<&cpu3_intc 11>, <&cpu3_intc 9>,
|
||||
<&cpu4_intc 11>, <&cpu4_intc 9>,
|
||||
<&cpu5_intc 11>, <&cpu5_intc 9>,
|
||||
<&cpu6_intc 11>, <&cpu6_intc 9>,
|
||||
<&cpu7_intc 11>, <&cpu7_intc 9>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
riscv,ndev = <159>;
|
||||
};
|
||||
|
||||
clint: timer@e4000000 {
|
||||
compatible = "spacemit,k1-clint", "sifive,clint0";
|
||||
reg = <0x0 0xe4000000 0x0 0x10000>;
|
||||
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
|
||||
<&cpu1_intc 3>, <&cpu1_intc 7>,
|
||||
<&cpu2_intc 3>, <&cpu2_intc 7>,
|
||||
<&cpu3_intc 3>, <&cpu3_intc 7>,
|
||||
<&cpu4_intc 3>, <&cpu4_intc 7>,
|
||||
<&cpu5_intc 3>, <&cpu5_intc 7>,
|
||||
<&cpu6_intc 3>, <&cpu6_intc 7>,
|
||||
<&cpu7_intc 3>, <&cpu7_intc 7>;
|
||||
};
|
||||
|
||||
sec_uart1: serial@f0612000 {
|
||||
compatible = "spacemit,k1-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xf0612000 0x0 0x100>;
|
||||
interrupts = <43>;
|
||||
clock-frequency = <14857000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "reserved"; /* for TEE usage */
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user