Proxmox-Port/linux-loongson
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson synced 2025-09-04 18:49:41 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes

Browse Source 
Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3
host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.

Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/20240801054803.3015572-3-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
devi priya 2024-08-01 11:18:01 +05:30 committed by Bjorn Andersson
parent 7069abcd53
commit d80c7fbfa9
1 changed files with 416 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

420
arch/arm64/boot/dts/qcom/ipq9574.dtsi
View File

@ -226,6 +226,52 @@ rpm_msg_ram: sram@60000 {
reg = <0x00060000 0x6000>;
};
pcie0_phy: phy@84000 {
compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
reg = <0x00084000 0x1000>;
clocks = <&gcc GCC_PCIE0_AUX_CLK>,
<&gcc GCC_PCIE0_AHB_CLK>,
<&gcc GCC_PCIE0_PIPE_CLK>;
clock-names = "aux", "cfg_ahb", "pipe";
assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
assigned-clock-rates = <20000000>;
resets = <&gcc GCC_PCIE0_PHY_BCR>,
<&gcc GCC_PCIE0PHY_PHY_BCR>;
reset-names = "phy", "common";
#clock-cells = <0>;
clock-output-names = "gcc_pcie0_pipe_clk_src";
#phy-cells = <0>;
status = "disabled";
};
pcie2_phy: phy@8c000 {
compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
reg = <0x0008c000 0x2000>;
clocks = <&gcc GCC_PCIE2_AUX_CLK>,
<&gcc GCC_PCIE2_AHB_CLK>,
<&gcc GCC_PCIE2_PIPE_CLK>;
clock-names = "aux", "cfg_ahb", "pipe";
assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
assigned-clock-rates = <20000000>;
resets = <&gcc GCC_PCIE2_PHY_BCR>,
<&gcc GCC_PCIE2PHY_PHY_BCR>;
reset-names = "phy", "common";
#clock-cells = <0>;
clock-output-names = "gcc_pcie2_pipe_clk_src";
#phy-cells = <0>;
status = "disabled";
};
rng: rng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x000e3000 0x1000>;
@ -243,6 +289,52 @@ mdio: mdio@90000 {
status = "disabled";
};
pcie3_phy: phy@f4000 {
compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
reg = <0x000f4000 0x2000>;
clocks = <&gcc GCC_PCIE3_AUX_CLK>,
<&gcc GCC_PCIE3_AHB_CLK>,
<&gcc GCC_PCIE3_PIPE_CLK>;
clock-names = "aux", "cfg_ahb", "pipe";
assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
assigned-clock-rates = <20000000>;
resets = <&gcc GCC_PCIE3_PHY_BCR>,
<&gcc GCC_PCIE3PHY_PHY_BCR>;
reset-names = "phy", "common";
#clock-cells = <0>;
clock-output-names = "gcc_pcie3_pipe_clk_src";
#phy-cells = <0>;
status = "disabled";
};
pcie1_phy: phy@fc000 {
compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
reg = <0x000fc000 0x1000>;
clocks = <&gcc GCC_PCIE1_AUX_CLK>,
<&gcc GCC_PCIE1_AHB_CLK>,
<&gcc GCC_PCIE1_PIPE_CLK>;
clock-names = "aux", "cfg_ahb", "pipe";
assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
assigned-clock-rates = <20000000>;
resets = <&gcc GCC_PCIE1_PHY_BCR>,
<&gcc GCC_PCIE1PHY_PHY_BCR>;
reset-names = "phy", "common";
#clock-cells = <0>;
clock-output-names = "gcc_pcie1_pipe_clk_src";
#phy-cells = <0>;
status = "disabled";
};
qfprom: efuse@a4000 {
compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
reg = <0x000a4000 0x5a1>;
@ -309,10 +401,10 @@ gcc: clock-controller@1800000 {
clocks = <&xo_board_clk>,
<&sleep_clk>,
<0>,
<0>,
<0>,
<0>,
<0>,
<&pcie0_phy>,
<&pcie1_phy>,
<&pcie2_phy>,
<&pcie3_phy>,
<0>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -756,6 +848,326 @@ frame@b128000 {
status = "disabled";
};
};
pcie1: pcie@10000000 {
compatible = "qcom,pcie-ipq9574";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
<0x10001000 0x1000>,
<0x000f8000 0x4000>,
<0x10100000 0x1000>;
reg-names = "dbi", "elbi", "atu", "parf", "config";
device_type = "pci";
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
<0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
<&gcc GCC_PCIE1_AXI_S_CLK>,
<&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE1_RCHNG_CLK>,
<&gcc GCC_PCIE1_AHB_CLK>,
<&gcc GCC_PCIE1_AUX_CLK>;
clock-names = "axi_m",
"axi_s",
"axi_bridge",
"rchng",
"ahb",
"aux";
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
<&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
<&gcc GCC_PCIE1_AXI_S_ARES>,
<&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
<&gcc GCC_PCIE1_AXI_M_ARES>,
<&gcc GCC_PCIE1_AUX_ARES>,
<&gcc GCC_PCIE1_AHB_ARES>;
reset-names = "pipe",
"sticky",
"axi_s_sticky",
"axi_s",
"axi_m_sticky",
"axi_m",
"aux",
"ahb";
phys = <&pcie1_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
<&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
};
pcie3: pcie@18000000 {
compatible = "qcom,pcie-ipq9574";
reg = <0x18000000 0xf1d>,
<0x18000f20 0xa8>,
<0x18001000 0x1000>,
<0x000f0000 0x4000>,
<0x18100000 0x1000>;
reg-names = "dbi", "elbi", "atu", "parf", "config";
device_type = "pci";
linux,pci-domain = <3>;
bus-range = <0x00 0xff>;
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>,
<0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
<&gcc GCC_PCIE3_AXI_S_CLK>,
<&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE3_RCHNG_CLK>,
<&gcc GCC_PCIE3_AHB_CLK>,
<&gcc GCC_PCIE3_AUX_CLK>;
clock-names = "axi_m",
"axi_s",
"axi_bridge",
"rchng",
"ahb",
"aux";
resets = <&gcc GCC_PCIE3_PIPE_ARES>,
<&gcc GCC_PCIE3_CORE_STICKY_ARES>,
<&gcc GCC_PCIE3_AXI_S_STICKY_ARES>,
<&gcc GCC_PCIE3_AXI_S_ARES>,
<&gcc GCC_PCIE3_AXI_M_STICKY_ARES>,
<&gcc GCC_PCIE3_AXI_M_ARES>,
<&gcc GCC_PCIE3_AUX_ARES>,
<&gcc GCC_PCIE3_AHB_ARES>;
reset-names = "pipe",
"sticky",
"axi_s_sticky",
"axi_s",
"axi_m_sticky",
"axi_m",
"aux",
"ahb";
phys = <&pcie3_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
<&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
};
pcie2: pcie@20000000 {
compatible = "qcom,pcie-ipq9574";
reg = <0x20000000 0xf1d>,
<0x20000f20 0xa8>,
<0x20001000 0x1000>,
<0x00088000 0x4000>,
<0x20100000 0x1000>;
reg-names = "dbi", "elbi", "atu", "parf", "config";
device_type = "pci";
linux,pci-domain = <2>;
bus-range = <0x00 0xff>;
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>,
<0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
<&gcc GCC_PCIE2_AXI_S_CLK>,
<&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE2_RCHNG_CLK>,
<&gcc GCC_PCIE2_AHB_CLK>,
<&gcc GCC_PCIE2_AUX_CLK>;
clock-names = "axi_m",
"axi_s",
"axi_bridge",
"rchng",
"ahb",
"aux";
resets = <&gcc GCC_PCIE2_PIPE_ARES>,
<&gcc GCC_PCIE2_CORE_STICKY_ARES>,
<&gcc GCC_PCIE2_AXI_S_STICKY_ARES>,
<&gcc GCC_PCIE2_AXI_S_ARES>,
<&gcc GCC_PCIE2_AXI_M_STICKY_ARES>,
<&gcc GCC_PCIE2_AXI_M_ARES>,
<&gcc GCC_PCIE2_AUX_ARES>,
<&gcc GCC_PCIE2_AHB_ARES>;
reset-names = "pipe",
"sticky",
"axi_s_sticky",
"axi_s",
"axi_m_sticky",
"axi_m",
"aux",
"ahb";
phys = <&pcie2_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
<&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
};
pcie0: pci@28000000 {
compatible = "qcom,pcie-ipq9574";
reg = <0x28000000 0xf1d>,
<0x28000f20 0xa8>,
<0x28001000 0x1000>,
<0x00080000 0x4000>,
<0x28100000 0x1000>;
reg-names = "dbi", "elbi", "atu", "parf", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>,
<0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
<&gcc GCC_PCIE0_AXI_S_CLK>,
<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE0_RCHNG_CLK>,
<&gcc GCC_PCIE0_AHB_CLK>,
<&gcc GCC_PCIE0_AUX_CLK>;
clock-names = "axi_m",
"axi_s",
"axi_bridge",
"rchng",
"ahb",
"aux";
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_S_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_S_ARES>,
<&gcc GCC_PCIE0_AXI_M_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_M_ARES>,
<&gcc GCC_PCIE0_AUX_ARES>,
<&gcc GCC_PCIE0_AHB_ARES>;
reset-names = "pipe",
"sticky",
"axi_s_sticky",
"axi_s",
"axi_m_sticky",
"axi_m",
"aux",
"ahb";
phys = <&pcie0_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
<&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
};
};
thermal-zones {