mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-04 18:49:41 +00:00
arm64: dts: add description for solidrun am642 som and evaluation board
Add description for the SolidRun AM642 SoM, and HummingBoard-T evaluation board. The SoM features: - 1x cpsw ethernet with phy - 2x pru ethernet with phy - eMMC - spi flash (assembly option) Additionally microSD and usb-2.0 otg are included in the SoM description as they are supported boot sources for the SOC boot-rom. The Carrier provides: - 3x RJ45 connector - 2x M.2 connector - USB-2.0 Hub - USB-A Connector - LEDs - 2x CAN transceiver - 1x RS485 transceiver - sensors The M.2 connectors support either USB-3.1 or PCI-E depending on status of a mux. By default the mux is switched off. Signed-off-by: Josua Mayer <josua@solid-run.com> Link: https://lore.kernel.org/r/20240219-add-am64-som-v7-3-0e6e95b0a05d@solid-run.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Josua Mayer
Vignesh Raghavendra
parent
d14bae4087
commit
d60483faf9
@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo
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# Boards with AM64x SoC
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb
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292
arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts
Normal file
292
arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts
Normal file
@ -0,0 +1,292 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
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*
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* DTS for SolidRun AM642 HummingBoard-T,
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* running on Cortex A53.
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*
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*/
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/dts-v1/;
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/phy/phy.h>
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#include "k3-am642.dtsi"
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#include "k3-am642-sr-som.dtsi"
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/ {
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model = "SolidRun AM642 HummingBoard-T";
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compatible = "solidrun,am642-hummingboard-t", "solidrun,am642-sr-som", "ti,am642";
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aliases {
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serial5 = &main_uart3;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&leds_default_pins>;
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/* D24 */
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led1: led-1 {
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label = "led1";
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gpios = <&main_gpio0 29 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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};
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/* D25 */
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led2: led-2 {
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label = "led2";
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gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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};
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/* D26 */
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led3: led-3 {
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label = "led3";
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gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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};
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};
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regulator-m2-3v3 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <®ulator_pcie_3v3_default_pins>;
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regulator-name = "m2-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&main_gpio1 17 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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regulator-vpp-1v8 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <®ulator_vpp_1v8_default_pins>;
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regulator-name = "vpp-1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&main_gpio1 78 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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serdes_mux: mux-controller {
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compatible = "gpio-mux";
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pinctrl-names = "default";
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pinctrl-0 = <&serdes_mux_default_pins>;
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#mux-control-cells = <0>;
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/*
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* Mux has 2 IOs:
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* - select: 0 = USB-3 (M2); 1 = PCIE (M1)
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* - shutdown: 0 = active; 1 = disabled (high impedance)
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*/
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mux-gpios = <&main_gpio1 40 GPIO_ACTIVE_HIGH>, <&main_gpio1 41 GPIO_ACTIVE_HIGH>;
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/* default disabled */
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idle-state = <2>;
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};
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};
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&main_gpio0 {
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m2-reset-hog {
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gpio-hog;
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gpios = <12 GPIO_ACTIVE_LOW>;
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output-low; /* deasserted */
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line-name = "m2-reset";
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};
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m1-m2-w-disable1-hog {
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gpio-hog;
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gpios = <32 GPIO_ACTIVE_LOW>;
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output-low; /* deasserted */
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line-name = "m1-m2-pcie-w-disable1";
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};
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m1-m2-w-disable2-hog {
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gpio-hog;
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gpios = <34 GPIO_ACTIVE_LOW>;
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output-low; /* deasserted */
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line-name = "m1-m2-pcie-w-disable2";
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};
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};
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&main_gpio1 {
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m1-pcie-clkreq0-hog {
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gpio-hog;
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gpios = <11 GPIO_ACTIVE_LOW>;
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input;
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line-name = "m1-pcie-clkreq0";
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};
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m2-pcie-clkreq-hog {
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gpio-hog;
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gpios = <35 GPIO_ACTIVE_LOW>;
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input;
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line-name = "m2-pcie-clkreq";
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};
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};
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&main_i2c0 {
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pinctrl-0 = <&main_i2c0_default_pins>, <&main_i2c0_int_default_pins>;
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humidity-sensor@41 {
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compatible = "ti,hdc2010";
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reg = <0x41>;
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interrupt-parent = <&main_gpio0>;
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interrupts = <37 IRQ_TYPE_EDGE_FALLING>;
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};
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light-sensor@44 {
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compatible = "ti,opt3001";
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reg = <0x44>;
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interrupt-parent = <&main_gpio0>;
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interrupts = <37 IRQ_TYPE_EDGE_FALLING>;
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};
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/* charger@6a */
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};
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&main_i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c1_default_pins>;
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status = "okay";
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rtc@69 {
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compatible = "abracon,abx80x";
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reg = <0x69>;
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pinctrl-names = "default";
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pinctrl-0 = <&rtc_int_default_pins>;
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abracon,tc-diode = "schottky";
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abracon,tc-resistor = <3>;
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interrupt-parent = <&main_gpio0>;
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interrupts = <44 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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&main_mcan0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_mcan0_default_pins>;
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status = "okay";
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can-transceiver {
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max-bitrate = <8000000>;
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};
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};
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&main_mcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_mcan1_default_pins>;
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status = "okay";
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can-transceiver {
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max-bitrate = <8000000>;
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};
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};
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&main_pmx0 {
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leds_default_pins: leds-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0074, PIN_OUTPUT, 7) /* GPMC0_AD14.GPIO0_29 */
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AM64X_IOPAD(0x0078, PIN_OUTPUT, 7) /* GPMC0_AD15.GPIO0_30 */
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AM64X_IOPAD(0x0088, PIN_OUTPUT, 7) /* GPMC0_OEn_REn.GPIO0_33 */
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>;
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};
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main_i2c0_int_default_pins: main-i2c0-int-default-pins {
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pinctrl-single,pins = <
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/* external pull-up on Carrier */
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AM64X_IOPAD(0x0098, PIN_INPUT, 7) /* GPMC0_WAIT0.GPIO0_37 */
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>;
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};
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main_i2c1_default_pins: main-i2c1-default-pins {
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pinctrl-single,pins = <
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/* external pull-up on SoM */
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AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* I2C1_SCL.I2C1_SCL */
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AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* I2C1_SDA.I2C1_SDA */
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>;
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};
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main_mcan0_default_pins: main-mcan0-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* MCAN0_RX.MCAN0_RX */
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AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* MCAN0_TX.MCAN0_TX */
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>;
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};
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main_mcan1_default_pins: main-mcan1-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* MCAN1_RX.MCAN1_RX */
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AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* MCAN1_TX.MCAN1_TX */
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>;
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};
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main_uart3_default_pins: main-uart3-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x016c, PIN_INPUT, 10) /* PRG0_PRU0_GPO3.UART3_CTSn */
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AM64X_IOPAD(0x0170, PIN_OUTPUT, 10) /* PRG0_PRU0_GPO4.UART3_TXD */
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AM64X_IOPAD(0x0174, PIN_OUTPUT, 10) /* PRG0_PRU0_GPO5.UART3_RTSn */
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AM64X_IOPAD(0x01ac, PIN_INPUT, 10) /* PRG0_PRU0_GPO19.UART3_RXD */
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>;
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};
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pcie0_default_pins: pcie0-default-pins {
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pinctrl-single,pins = <
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/* connector M2 RESET */
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AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* OSPI0_CSn1.GPIO0_12 */
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/* connectors M1 & M2 W_DISABLE1 */
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AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* GPMC0_ADVN_ALE.GPIO0_32 */
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/* connectors M1 & M2 W_DISABLE2 */
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AM64X_IOPAD(0x008c, PIN_OUTPUT, 7) /* GPMC0_WEN.GPIO0_34 */
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/* connectors M1 & M2 PERST0 (PCI Reset) */
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AM64X_IOPAD(0x019c, PIN_OUTPUT, 7) /* PRG0_PRU0_GPO15.GPIO1_15 */
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/* connector M1 CLKREQ0 */
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AM64X_IOPAD(0x018c, PIN_INPUT, 7) /* PRG0_PRU0_GPO11.GPIO1_11 */
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/* connector M2 CLKREQ0 */
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AM64X_IOPAD(0x01ec, PIN_INPUT, 7) /* PRG0_PRU1_GPO15.GPIO1_35 */
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>;
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};
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regulator_pcie_3v3_default_pins: regulator-pcie-3v3-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01a4, PIN_OUTPUT, 7) /* PRG0_PRU0_GPO17.GPIO1_17 */
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>;
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};
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regulator_vpp_1v8_default_pins: regulator-vpp-1v8-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x029c, PIN_OUTPUT, 7) /* MMC1_SDWP.GPIO1_78 */
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>;
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};
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rtc_int_default_pins: rtc-int-default-pins {
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pinctrl-single,pins = <
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/* external pull-up on Carrier */
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AM64X_IOPAD(0x00b4, PIN_INPUT, 7) /* GPMC0_CSn3.GPIO0_44 */
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>;
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};
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serdes_mux_default_pins: serdes-mux-default-pins {
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pinctrl-single,pins = <
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/* SEL, 10k pull-down on carrier, 2.2k pullup on SoM */
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AM64X_IOPAD(0x0200, PIN_OUTPUT, 7) /* PRG0_MDIO0_MDIO.GPIO1_40 */
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/* EN */
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AM64X_IOPAD(0x0204, PIN_OUTPUT, 7) /* PRG0_MDIO0_MDC.GPIO1_41 */
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>;
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};
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};
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&main_uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart3_default_pins>;
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uart-has-rtscts;
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rs485-rts-active-low;
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linux,rs485-enabled-at-boot-time;
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status = "okay";
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};
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&usb0 {
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dr_mode = "host";
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};
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594
arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
Normal file
594
arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
Normal file
@ -0,0 +1,594 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
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*
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*/
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#include <dt-bindings/net/ti-dp83869.h>
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/ {
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model = "SolidRun AM642 SoM";
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compatible = "solidrun,am642-sr-som", "ti,am642";
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aliases {
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ethernet0 = &cpsw_port1;
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ethernet1 = &icssg1_emac0;
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ethernet2 = &icssg1_emac1;
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mmc0 = &sdhci0;
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mmc1 = &sdhci1;
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serial2 = &main_uart0;
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};
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chosen {
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/* SoC default UART console */
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stdout-path = "serial2:115200n8";
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};
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/* PRU Ethernet Controller */
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ethernet {
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compatible = "ti,am642-icssg-prueth";
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pinctrl-names = "default";
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pinctrl-0 = <&pru_rgmii1_default_pins>, <&pru_rgmii2_default_pins>;
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sram = <&oc_sram>;
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ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
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firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
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"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
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"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
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/* configure internal pinmux for mii mode */
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ti,pruss-gp-mux-sel = <2>, <2>, <2>, <2>, <2>, <2>;
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ti,mii-g-rt = <&icssg1_mii_g_rt>;
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ti,mii-rt = <&icssg1_mii_rt>;
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ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
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/*
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* Configure icssg interrupt controller to map pru-internal
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* interrupts 8/9 via channels 0/1 to host interrupts 0/1.
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*
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* For details see interrupt controller documentation:
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* Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml
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*/
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interrupt-parent = <&icssg1_intc>;
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interrupts = <24 0 2>, <25 1 3>;
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interrupt-names = "tx_ts0", "tx_ts1";
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dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
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<&main_pktdma 0xc201 15>, /* egress slice 0 */
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<&main_pktdma 0xc202 15>, /* egress slice 0 */
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<&main_pktdma 0xc203 15>, /* egress slice 0 */
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<&main_pktdma 0xc204 15>, /* egress slice 1 */
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<&main_pktdma 0xc205 15>, /* egress slice 1 */
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<&main_pktdma 0xc206 15>, /* egress slice 1 */
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<&main_pktdma 0xc207 15>, /* egress slice 1 */
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<&main_pktdma 0x4200 15>, /* ingress slice 0 */
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<&main_pktdma 0x4201 15>; /* ingress slice 1 */
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dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
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"tx1-0", "tx1-1", "tx1-2", "tx1-3",
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"rx0", "rx1";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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icssg1_emac0: port@0 {
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reg = <0>;
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ti,syscon-rgmii-delay = <&main_conf 0x4110>;
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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phy-handle = <ðernet_phy2>;
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phy-mode = "rgmii-id";
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};
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icssg1_emac1: port@1 {
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reg = <1>;
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ti,syscon-rgmii-delay = <&main_conf 0x4114>;
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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phy-handle = <ðernet_phy1>;
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phy-mode = "rgmii-id";
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};
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||||
};
|
||||
};
|
||||
|
||||
/* DDR16SS0:
|
||||
* - Bank 1 @ 0x080000000-0x0FFFFFFFF: max. 2GB in 32-bit address space
|
||||
* - Bank 2 @ 0x880000000-0x9FFFFFFFF: max. 6GB in 64-bit address space
|
||||
*/
|
||||
memory@80000000 {
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000001 0x80000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_mmc0: regulator-vdd-mmc0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd-mmc0";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii1_default_pins>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio0_default_pins>;
|
||||
status = "okay";
|
||||
|
||||
ethernet_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id2000.a0f1";
|
||||
reg = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ðernet_phy0_default_pins>;
|
||||
ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
|
||||
ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
|
||||
/*
|
||||
* Disable interrupts because ISR never clears 0x0040
|
||||
*
|
||||
* interrupt-parent = <&main_gpio1>;
|
||||
* interrupts = <70 IRQ_TYPE_LEVEL_LOW>;
|
||||
*/
|
||||
/*
|
||||
* Disable HW Reset because clock signal is daisy-chained
|
||||
*
|
||||
* reset-gpios = <&main_gpio0 84 GPIO_ACTIVE_LOW>;
|
||||
* reset-assert-us = <1>;
|
||||
* reset-deassert-us = <30>;
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy0>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg1_mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pru1_mdio0_default_pins>;
|
||||
status = "okay";
|
||||
|
||||
ethernet_phy1: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-id2000.a0f1";
|
||||
reg = <3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ðernet_phy1_default_pins>;
|
||||
ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
|
||||
ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
|
||||
/*
|
||||
* Disable interrupts because ISR never clears 0x0040
|
||||
*
|
||||
* interrupt-parent = <&main_gpio1>;
|
||||
* interrupts = <70 IRQ_TYPE_LEVEL_LOW>;
|
||||
*/
|
||||
/*
|
||||
* Disable HW Reset because clock signal is daisy-chained
|
||||
*
|
||||
* reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>;
|
||||
* reset-assert-us = <1>;
|
||||
* reset-deassert-us = <30>;
|
||||
*/
|
||||
};
|
||||
|
||||
ethernet_phy2: ethernet-phy@f {
|
||||
compatible = "ethernet-phy-id2000.a0f1";
|
||||
reg = <0xf>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ðernet_phy2_default_pins>;
|
||||
ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
|
||||
/*
|
||||
* Disable interrupts because ISR never clears 0x0040
|
||||
*
|
||||
* interrupt-parent = <&main_gpio1>;
|
||||
* interrupts = <70 IRQ_TYPE_LEVEL_LOW>;
|
||||
*/
|
||||
/*
|
||||
* Disable HW Reset because clock signal is daisy-chained
|
||||
*
|
||||
* reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>;
|
||||
* reset-assert-us = <1>;
|
||||
* reset-deassert-us = <30>;
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_default_pins>;
|
||||
status = "okay";
|
||||
|
||||
som_eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c01";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
/* hog global functions */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ðernet_phy_default_pins>;
|
||||
|
||||
ethernet_phy_default_pins: ethernet-phy-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
/* interrupt / power-down, external pull-up on SoM */
|
||||
AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* EXTINTn.GPIO1_70 */
|
||||
>;
|
||||
};
|
||||
|
||||
ethernet_phy0_default_pins: ethernet-phy0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
/* reset */
|
||||
AM64X_IOPAD(0x0154, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO19.GPIO0_84 */
|
||||
/* reference clock */
|
||||
AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* EXT_REFCLK1.CLKOUT0 */
|
||||
>;
|
||||
};
|
||||
|
||||
ethernet_phy1_default_pins: ethernet-phy1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
/* reset */
|
||||
AM64X_IOPAD(0x0150, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO18.GPIO0_20 */
|
||||
/* led0, external pull-down on SoM */
|
||||
AM64X_IOPAD(0x0128, PIN_INPUT, 7) /* PRG1_PRU1_GPO8.GPIO0_73 */
|
||||
/* led1/rxer */
|
||||
AM64X_IOPAD(0x011c, PIN_INPUT, 7) /* PRG1_PRU1_GPO5.GPIO0_70 */
|
||||
>;
|
||||
};
|
||||
|
||||
ethernet_phy2_default_pins: ethernet-phy2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
/* reset */
|
||||
AM64X_IOPAD(0x00d4, PIN_OUTPUT, 7) /* PRG1_PRU0_GPO7.GPIO0_52 */
|
||||
/* led0, external pull-down on SoM */
|
||||
AM64X_IOPAD(0x00d8, PIN_INPUT, 7) /* PRG1_PRU0_GPO8.GPIO0_53 */
|
||||
/* led1/rxer */
|
||||
AM64X_IOPAD(0x00cc, PIN_INPUT, 7) /* PRG1_PRU0_GPO5.GPIO0_50 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c0_default_pins: main-i2c0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
/* external pull-up on SoM */
|
||||
AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* I2C0_SCL.I2C0_SCL */
|
||||
AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* I2C0_SDA.I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
/*
|
||||
* main_mmc0_default_pins: main-mmc0-default-pins
|
||||
*
|
||||
* MMC0_CMD: no padconfig
|
||||
* MMC0_CLK: no padconfig, external pull-up on SoM
|
||||
* MMC0_DAT0: no padconfig
|
||||
* MMC0_DAT1: no padconfig
|
||||
* MMC0_DAT2: no padconfig
|
||||
* MMC0_DAT3: no padconfig
|
||||
* MMC0_DAT4: no padconfig
|
||||
* MMC0_DAT5: no padconfig
|
||||
* MMC0_DAT6: no padconfig
|
||||
* MMC0_DAT7: no padconfig
|
||||
* MMC0_DS: no padconfig, external pull-down on SoM
|
||||
*/
|
||||
|
||||
main_mmc1_default_pins: main-mmc1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* MMC1_CLK.MMC1_CLK */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* MMC1_DAT0.MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* MMC1_DAT1.MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* MMC1_DAT2.MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* MMC1_DAT3.MMC1_DAT3 */
|
||||
/* external pull-down on SoM & Carrier */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* MMC1_SDCD.MMC1_SDCD */
|
||||
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB: clock loopback */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart0_default_pins: main-uart0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* UART0_RXD.UART0_RXD */
|
||||
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* UART0_TXD.UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
mdio0_default_pins: mdio0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* PRG0_PRU1_GPO19.MDIO0_MDC */
|
||||
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* PRG0_PRU1_GPO18.MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_default_pins: ospi0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
/* external pull-down on SoM */
|
||||
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* OSPI0_CLK.OSPI0_CLK */
|
||||
AM64X_IOPAD(0x0008, PIN_OUTPUT, 0) /* OSPI0_DQS.OSPI0_DQS */
|
||||
/* external pull-up on SoM */
|
||||
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* OSPI0_CSn0.OSPI0_CSn0 */
|
||||
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* OSPI0_D0.OSPI0_D0 */
|
||||
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* OSPI0_D1.OSPI0_D1 */
|
||||
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* OSPI0_D2.OSPI0_D2 */
|
||||
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* OSPI0_D3.OSPI0_D3 */
|
||||
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* OSPI0_D4.OSPI0_D4 */
|
||||
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* OSPI0_D5.OSPI0_D5 */
|
||||
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* OSPI0_D6.OSPI0_D6 */
|
||||
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* OSPI0_D7.OSPI0_D7 */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_flash0_default_pins: ospi0-flash0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0034, PIN_OUTPUT, 7) /* OSPI0_CSn2.GPIO0_13 */
|
||||
AM64X_IOPAD(0x0038, PIN_INPUT, 7) /* OSPI0_CSn3.GPIO0_14 */
|
||||
>;
|
||||
};
|
||||
|
||||
pru1_mdio0_default_pins: pru1-mdio0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* PRG1_MDIO0_MDC.PRG1_MDIO0_MDC */
|
||||
AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* PRG1_MDIO0_MDIO.PRG1_MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
pru_rgmii1_default_pins: pru-rgmii1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
|
||||
AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
|
||||
AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
|
||||
AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
|
||||
AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
|
||||
AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
|
||||
AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
|
||||
AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
|
||||
AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
|
||||
AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
|
||||
AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
|
||||
AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
pru_rgmii2_default_pins: pru-rgmii2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* PRG1_PRU1_GPO0.RGMII2_RD0 */
|
||||
AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* PRG1_PRU1_GPO1.RGMII2_RD1 */
|
||||
AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* PRG1_PRU1_GPO2.RGMII2_RD2 */
|
||||
AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* PRG1_PRU1_GPO3.RGMII2_RD3 */
|
||||
AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* PRG1_PRU1_GPO6.RGMII2_RXC */
|
||||
AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* PRG1_PRU1_GPO4.RGMII2_RX_CTL */
|
||||
AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO11.RGMII2_TD0 */
|
||||
AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO12.RGMII2_TD1 */
|
||||
AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO13.RGMII2_TD2 */
|
||||
AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO14.RGMII2_TD3 */
|
||||
AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* PRG1_PRU1_GPO16.RGMII2_TXC */
|
||||
AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO15.RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii1_default_pins: rgmii1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* PRG0_PRU1_GPO7.RGMII1_RD0 */
|
||||
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* PRG0_PRU1_GPO9.RGMII1_RD1 */
|
||||
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* PRG0_PRU1_GPO10.RGMII1_RD2 */
|
||||
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* PRG0_PRU1_GPO17.RGMII1_RD3 */
|
||||
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* PRG0_PRU0_GPO10.RGMII1_RXC */
|
||||
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* PRG0_PRU0_GPO9.RGMII1_RX_CTL */
|
||||
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO7.RGMII1_TD0 */
|
||||
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO9.RGMII1_TD1 */
|
||||
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO10.RGMII1_TD2 */
|
||||
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO17.RGMII1_TD3 */
|
||||
AM64X_IOPAD(0x00e0, PIN_INPUT, 4) /* PRG1_PRU0_GPO10.RGMII1_TXC */
|
||||
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* PRG1_PRU0_GPO9.RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
usb0_default_pins: usb0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
/* SoC default UART console */
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_default_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_default_pins>;
|
||||
num-cs = <1>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_flash0_default_pins>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <200000000>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
cdns,tslch-ns = <4>;
|
||||
cdns,read-delay = <0>;
|
||||
interrupt-parent = <&main_gpio0>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&main_gpio0 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
/* mmc0 pins have no padconfig */
|
||||
bus-width = <8>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
cap-mmc-hw-reset;
|
||||
no-sd;
|
||||
/*
|
||||
* MMC controller supports switching between 1.8V and 3.3V signalling.
|
||||
* However MMC0 (unlike MMC1) does not integrate an LDO.
|
||||
* Explicitly link a regulator node for indicating to the driver which
|
||||
* voltages are actually usable.
|
||||
*/
|
||||
vqmmc-supply = <&vdd_mmc0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* microSD is on carrier - however since SoC can boot from it,
|
||||
* configure it just in case.
|
||||
*/
|
||||
&sdhci1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_default_pins>;
|
||||
bus-width = <4>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* USB settings are a carrier choice - however since SoC can boot from it,
|
||||
* configure as USB-2.0 OTG here, keeping USB-3 serdes disabled.
|
||||
*/
|
||||
&usb0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb0_default_pins>;
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,vbus-divider;
|
||||
ti,usb2-only;
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user