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scsi: ufs: exynos: Add support for Tensor gs101 SoC
Add a dedicated compatible and drv_data with associated hooks for gs101 SoC found on Pixel 6. Note we make use of the previously added EXYNOS_UFS_OPT_UFSPR_SECURE option, to skip initialisation of UFSPR registers as these are only accessible via SMC call. EXYNOS_UFS_OPT_TIMER_TICK_SELECT option is also set to select tick source. This has been done so as not to effect any existing platforms. DBG_OPTION_SUITE on gs101 has different address offsets to other SoCs so these register offsets now come from uic_attr struct. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240426122004.2249178-7-peter.griffin@linaro.org Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Peter Griffin
Martin K. Petersen
parent
6f9f0d564b
commit
d11e0a318d
@ -61,6 +61,7 @@
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#define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\
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UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
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UNIPRO_PCLK_STOP)
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/* HCI_MISC is also known as HCI_FORCE_HCS */
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#define HCI_MISC 0xB4
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#define REFCLK_CTRL_EN BIT(7)
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#define UNIPRO_PCLK_CTRL_EN BIT(6)
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@ -138,6 +139,9 @@ enum {
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/*
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* UNIPRO registers
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*/
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#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0 0x7888
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#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1 0x788c
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#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2 0x7890
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#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0 0x78B8
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#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1 0x78BC
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#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2 0x78C0
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@ -938,6 +942,10 @@ static void exynos_ufs_config_unipro(struct exynos_ufs *ufs)
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if (attr->pa_dbg_opt_suite1_off)
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ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off),
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attr->pa_dbg_opt_suite1_val);
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if (attr->pa_dbg_opt_suite2_off)
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ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite2_off),
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attr->pa_dbg_opt_suite2_val);
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}
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static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
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@ -1593,6 +1601,96 @@ static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
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return 0;
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}
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static inline u32 get_mclk_period_unipro_18(struct exynos_ufs *ufs)
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{
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return (16 * 1000 * 1000000UL / ufs->mclk_rate);
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}
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static int gs101_ufs_pre_link(struct exynos_ufs *ufs)
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{
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struct ufs_hba *hba = ufs->hba;
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int i;
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u32 tx_line_reset_period, rx_line_reset_period;
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rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate)
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/ NSEC_PER_MSEC;
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tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate)
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/ NSEC_PER_MSEC;
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unipro_writel(ufs, get_mclk_period_unipro_18(ufs), COMP_CLK_PERIOD);
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
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for_each_ufs_rx_lane(ufs, i) {
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i),
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DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i),
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(rx_line_reset_period >> 16) & 0xFF);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i),
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(rx_line_reset_period >> 8) & 0xFF);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i),
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(rx_line_reset_period) & 0xFF);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x69);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
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}
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for_each_ufs_tx_lane(ufs, i) {
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i),
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DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i),
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0x02);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i),
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(tx_line_reset_period >> 16) & 0xFF);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i),
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(tx_line_reset_period >> 8) & 0xFF);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i),
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(tx_line_reset_period) & 0xFF);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7F, i), 0);
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}
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED);
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ufshcd_dme_set(hba, UIC_ARG_MIB(0xA006), 0x8000);
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return 0;
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}
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static int gs101_ufs_post_link(struct exynos_ufs *ufs)
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{
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struct ufs_hba *hba = ufs->hba;
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exynos_ufs_enable_dbg_mode(hba);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8);
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exynos_ufs_disable_dbg_mode(hba);
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return 0;
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}
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static int gs101_ufs_pre_pwr_change(struct exynos_ufs *ufs,
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struct ufs_pa_layer_attr *pwr)
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{
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struct ufs_hba *hba = ufs->hba;
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
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unipro_writel(ufs, 8064, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0);
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unipro_writel(ufs, 28224, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1);
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unipro_writel(ufs, 20160, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2);
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unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0);
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unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1);
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unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2);
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return 0;
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}
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static const struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
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.name = "exynos_ufs",
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.init = exynos_ufs_init,
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@ -1720,6 +1818,34 @@ static const struct exynos_ufs_drv_data exynos_ufs_drvs = {
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.post_pwr_change = exynos7_ufs_post_pwr_change,
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};
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static struct exynos_ufs_uic_attr gs101_uic_attr = {
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.tx_trailingclks = 0xff,
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.tx_dif_p_nsec = 3000000, /* unit: ns */
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.tx_dif_n_nsec = 1000000, /* unit: ns */
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.tx_high_z_cnt_nsec = 20000, /* unit: ns */
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.tx_base_unit_nsec = 100000, /* unit: ns */
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.tx_gran_unit_nsec = 4000, /* unit: ns */
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.tx_sleep_cnt = 1000, /* unit: ns */
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.tx_min_activatetime = 0xa,
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.rx_filler_enable = 0x2,
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.rx_dif_p_nsec = 1000000, /* unit: ns */
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.rx_hibern8_wait_nsec = 4000000, /* unit: ns */
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.rx_base_unit_nsec = 100000, /* unit: ns */
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.rx_gran_unit_nsec = 4000, /* unit: ns */
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.rx_sleep_cnt = 1280, /* unit: ns */
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.rx_stall_cnt = 320, /* unit: ns */
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.rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
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.rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
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.rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
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.rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
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.rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
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.rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
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.pa_dbg_opt_suite1_val = 0x90913C1C,
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.pa_dbg_opt_suite1_off = PA_GS101_DBG_OPTION_SUITE1,
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.pa_dbg_opt_suite2_val = 0xE01C115F,
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.pa_dbg_opt_suite2_off = PA_GS101_DBG_OPTION_SUITE2,
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};
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static struct exynos_ufs_uic_attr fsd_uic_attr = {
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.tx_trailingclks = 0x10,
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.tx_dif_p_nsec = 3000000, /* unit: ns */
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@ -1763,7 +1889,27 @@ static const struct exynos_ufs_drv_data fsd_ufs_drvs = {
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.pre_pwr_change = fsd_ufs_pre_pwr_change,
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};
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static const struct exynos_ufs_drv_data gs101_ufs_drvs = {
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.uic_attr = &gs101_uic_attr,
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.quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
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UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
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UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
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UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
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UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL |
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UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
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.opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
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EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
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EXYNOS_UFS_OPT_UFSPR_SECURE |
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EXYNOS_UFS_OPT_TIMER_TICK_SELECT,
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.drv_init = exynosauto_ufs_drv_init,
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.pre_link = gs101_ufs_pre_link,
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.post_link = gs101_ufs_post_link,
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.pre_pwr_change = gs101_ufs_pre_pwr_change,
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};
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static const struct of_device_id exynos_ufs_of_match[] = {
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{ .compatible = "google,gs101-ufs",
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.data = &gs101_ufs_drvs },
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{ .compatible = "samsung,exynos7-ufs",
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.data = &exynos_ufs_drvs },
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{ .compatible = "samsung,exynosautov9-ufs",
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@ -9,6 +9,12 @@
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#ifndef _UFS_EXYNOS_H_
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#define _UFS_EXYNOS_H_
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/*
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* Component registers
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*/
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#define COMP_CLK_PERIOD 0x44
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/*
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* UNIPRO registers
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*/
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@ -29,6 +35,14 @@
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#define PA_DBG_OPTION_SUITE 0x9564
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#define PA_DBG_OPTION_SUITE_DYN 0x9565
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/*
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* Note: GS101_DBG_OPTION offsets below differ from the TRM
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* but match the downstream driver. Following the TRM
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* results in non-functioning UFS.
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*/
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#define PA_GS101_DBG_OPTION_SUITE1 0x956a
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#define PA_GS101_DBG_OPTION_SUITE2 0x956d
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/*
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* MIBs for Transport Layer debug registers
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*/
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