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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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arm64: dts: qcom: sm8550: add adsp, cdsp & mdss nodes
This adds support for the aDSP, cDSP and MPSS Subsystems found in the SM8550 SoC. The aDSP, cDSP and MPSS needs: - smp2p nodes to get event back from the subsystems - remoteproc nodes with glink-edge subnodes providing all needed resources to start and run the subsystems In addition, the MPSS Subsystem needs a rmtfs_mem dedicated memory zone. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-remoteproc-v3-2-815a1753de34@linaro.org
This commit is contained in:
Neil Armstrong
Bjorn Andersson
parent
2e3790de9b
commit
d0c061e366
@ -542,6 +542,15 @@ adspslpi_mem: adspslpi-region@9ea00000 {
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/* Linux kernel image is loaded at 0xa8000000 */
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rmtfs_mem: rmtfs-region@d4a80000 {
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compatible = "qcom,rmtfs-mem";
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reg = <0x0 0xd4a80000 0x0 0x280000>;
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no-map;
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qcom,client-id = <1>;
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qcom,vmid = <15>;
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};
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mpss_dsm_mem: mpss-dsm-region@d4d00000 {
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reg = <0 0xd4d00000 0 0x3300000>;
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no-map;
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@ -633,6 +642,89 @@ hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
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};
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};
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smp2p-adsp {
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compatible = "qcom,smp2p";
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qcom,smem = <443>, <429>;
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interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <2>;
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smp2p_adsp_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_adsp_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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smp2p-cdsp {
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compatible = "qcom,smp2p";
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qcom,smem = <94>, <432>;
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interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
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IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_CDSP
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <5>;
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smp2p_cdsp_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_cdsp_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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smp2p-modem {
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compatible = "qcom,smp2p";
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qcom,smem = <435>, <428>;
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interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
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IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_MPSS
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <1>;
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smp2p_modem_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_modem_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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ipa_smp2p_out: ipa-ap-to-modem {
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qcom,entry-name = "ipa";
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#qcom,smem-state-cells = <1>;
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};
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ipa_smp2p_in: ipa-modem-to-ap {
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qcom,entry-name = "ipa";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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soc: soc@0 {
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compatible = "simple-bus";
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ranges = <0 0 0 0 0x10 0>;
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@ -1654,6 +1746,48 @@ tcsr: clock-controller@1fc0000 {
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#reset-cells = <1>;
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};
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remoteproc_mpss: remoteproc@4080000 {
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compatible = "qcom,sm8550-mpss-pas";
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reg = <0x0 0x04080000 0x0 0x4040>;
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interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready", "handover",
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"stop-ack", "shutdown-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd SM8550_CX>,
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<&rpmhpd SM8550_MSS>;
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power-domain-names = "cx", "mss";
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interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
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memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&smp2p_modem_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_MPSS
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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label = "mpss";
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qcom,remote-pid = <1>;
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};
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};
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lpass_lpiaon_noc: interconnect@7400000 {
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compatible = "qcom,sm8550-lpass-lpiaon-noc";
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reg = <0 0x07400000 0 0x19080>;
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@ -3000,12 +3134,214 @@ system-cache-controller@25000000 {
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interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
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};
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remoteproc_adsp: remoteproc@30000000 {
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compatible = "qcom,sm8550-adsp-pas";
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reg = <0x0 0x30000000 0x0 0x100>;
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interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd SM8550_LCX>,
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<&rpmhpd SM8550_LMX>;
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power-domain-names = "lcx", "lmx";
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interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
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memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&smp2p_adsp_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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remoteproc_adsp_glink: glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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label = "lpass";
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qcom,remote-pid = <2>;
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fastrpc {
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compatible = "qcom,fastrpc";
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qcom,glink-channels = "fastrpcglink-apps-dsp";
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label = "adsp";
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#address-cells = <1>;
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#size-cells = <0>;
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compute-cb@3 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <3>;
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iommus = <&apps_smmu 0x1003 0x80>,
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<&apps_smmu 0x1063 0x0>;
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};
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compute-cb@4 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <4>;
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iommus = <&apps_smmu 0x1004 0x80>,
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<&apps_smmu 0x1064 0x0>;
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};
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compute-cb@5 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <5>;
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iommus = <&apps_smmu 0x1005 0x80>,
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<&apps_smmu 0x1065 0x0>;
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};
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compute-cb@6 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <6>;
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iommus = <&apps_smmu 0x1006 0x80>,
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<&apps_smmu 0x1066 0x0>;
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};
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compute-cb@7 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <7>;
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iommus = <&apps_smmu 0x1007 0x80>,
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<&apps_smmu 0x1067 0x0>;
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};
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};
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};
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};
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nsp_noc: interconnect@320c0000 {
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compatible = "qcom,sm8550-nsp-noc";
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reg = <0 0x320c0000 0 0xe080>;
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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remoteproc_cdsp: remoteproc@32300000 {
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compatible = "qcom,sm8550-cdsp-pas";
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reg = <0x0 0x32300000 0x0 0x1400000>;
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interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd SM8550_CX>,
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<&rpmhpd SM8550_MXC>,
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<&rpmhpd SM8550_NSP>;
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power-domain-names = "cx", "mxc", "nsp";
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interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
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memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&smp2p_cdsp_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_CDSP
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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label = "cdsp";
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qcom,remote-pid = <5>;
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fastrpc {
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compatible = "qcom,fastrpc";
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qcom,glink-channels = "fastrpcglink-apps-dsp";
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label = "cdsp";
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#address-cells = <1>;
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#size-cells = <0>;
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compute-cb@1 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <1>;
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iommus = <&apps_smmu 0x1961 0x0>,
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<&apps_smmu 0x0c01 0x20>,
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<&apps_smmu 0x19c1 0x10>;
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};
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compute-cb@2 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <2>;
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iommus = <&apps_smmu 0x1962 0x0>,
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<&apps_smmu 0x0c02 0x20>,
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<&apps_smmu 0x19c2 0x10>;
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};
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compute-cb@3 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <3>;
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iommus = <&apps_smmu 0x1963 0x0>,
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<&apps_smmu 0x0c03 0x20>,
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<&apps_smmu 0x19c3 0x10>;
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};
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compute-cb@4 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <4>;
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iommus = <&apps_smmu 0x1964 0x0>,
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<&apps_smmu 0x0c04 0x20>,
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<&apps_smmu 0x19c4 0x10>;
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};
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compute-cb@5 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <5>;
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iommus = <&apps_smmu 0x1965 0x0>,
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<&apps_smmu 0x0c05 0x20>,
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<&apps_smmu 0x19c5 0x10>;
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};
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compute-cb@6 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <6>;
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iommus = <&apps_smmu 0x1966 0x0>,
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<&apps_smmu 0x0c06 0x20>,
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<&apps_smmu 0x19c6 0x10>;
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};
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compute-cb@7 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <7>;
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iommus = <&apps_smmu 0x1967 0x0>,
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<&apps_smmu 0x0c07 0x20>,
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<&apps_smmu 0x19c7 0x10>;
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};
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compute-cb@8 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <8>;
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iommus = <&apps_smmu 0x1968 0x0>,
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<&apps_smmu 0x0c08 0x20>,
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<&apps_smmu 0x19c8 0x10>;
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};
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/* note: secure cb9 in downstream */
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};
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};
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};
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};
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thermal-zones {
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