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arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK

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Add basic support for the RZ/G2LC SMARC EVK (based on R9A07G044C2):
- memory
- External input clock
- SCIF
- GbEthernet
- Audio Clock

It shares the same carrier board with RZ/G2L, but the pin mapping is
different.  Disable the device nodes which are not tested and delete the
corresponding pinctrl definitions.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211216114305.5842-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2021-12-16 11:43:05 +00:00 committed by Geert Uytterhoeven
parent 3a3c2a48d8
commit ce0c63b6a5
4 changed files with 216 additions and 0 deletions
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1
arch/arm64/boot/dts/renesas/Makefile
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@ -75,4 +75,5 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb

114
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts Normal file
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@ -0,0 +1,114 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC SMARC EVK board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a07g044c2.dtsi"
#include "rzg2lc-smarc-som.dtsi"
#include "rzg2lc-smarc-pinfunction.dtsi"
#include "rzg2l-smarc.dtsi"
/ {
model = "Renesas SMARC EVK based on r9a07g044c2";
compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
};
&canfd {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ehci0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ehci1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&hsusb {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&i2c0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&i2c1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&i2c3 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ohci0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ohci1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&phyrst {
status = "disabled";
};
&scif2 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&sdhi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-1;
/delete-property/ pinctrl-names;
/delete-property/ vmmc-supply;
status = "disabled";
};
&spi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ssi0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&usb2_phy0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&usb2_phy1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};

25
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi Normal file
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@ -0,0 +1,25 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC SMARC pincontrol parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
&pinctrl {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
sound_clk_pins: sound_clk {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
};
};

76
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi Normal file
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@ -0,0 +1,76 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC SMARC SOM common parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/ {
aliases {
ethernet0 = &eth0;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
};
&eth0 {
pinctrl-0 = <&eth0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
&extal_clk {
clock-frequency = <24000000>;
};
&pinctrl {
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
};
};