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arm64: dts: qcom: sm8350: Add cpufreq node

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Add cpufreq node and reference it for the CPUs.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210216111703.1838663-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Vinod Koul 2021-02-16 16:47:03 +05:30 committed by Bjorn Andersson
parent 6d91e20111
commit ccbb3abb23
1 changed files with 21 additions and 0 deletions
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21
arch/arm64/boot/dts/qcom/sm8350.dtsi
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@ -44,6 +44,7 @@ CPU0: cpu@0 {
reg = <0x0 0x0>; reg = <0x0 0x0>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache { L2_0: l2-cache {
compatible = "cache"; compatible = "cache";
next-level-cache = <&L3_0>; next-level-cache = <&L3_0>;
@ -59,6 +60,7 @@ CPU1: cpu@100 {
reg = <0x0 0x100>; reg = <0x0 0x100>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_100>; next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache { L2_100: l2-cache {
compatible = "cache"; compatible = "cache";
next-level-cache = <&L3_0>; next-level-cache = <&L3_0>;
@ -71,6 +73,7 @@ CPU2: cpu@200 {
reg = <0x0 0x200>; reg = <0x0 0x200>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_200>; next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache { L2_200: l2-cache {
compatible = "cache"; compatible = "cache";
next-level-cache = <&L3_0>; next-level-cache = <&L3_0>;
@ -83,6 +86,7 @@ CPU3: cpu@300 {
reg = <0x0 0x300>; reg = <0x0 0x300>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_300>; next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache { L2_300: l2-cache {
compatible = "cache"; compatible = "cache";
next-level-cache = <&L3_0>; next-level-cache = <&L3_0>;
@ -95,6 +99,7 @@ CPU4: cpu@400 {
reg = <0x0 0x400>; reg = <0x0 0x400>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_400>; next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_400: l2-cache { L2_400: l2-cache {
compatible = "cache"; compatible = "cache";
next-level-cache = <&L3_0>; next-level-cache = <&L3_0>;
@ -107,6 +112,7 @@ CPU5: cpu@500 {
reg = <0x0 0x500>; reg = <0x0 0x500>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_500>; next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_500: l2-cache { L2_500: l2-cache {
compatible = "cache"; compatible = "cache";
next-level-cache = <&L3_0>; next-level-cache = <&L3_0>;
@ -120,6 +126,7 @@ CPU6: cpu@600 {
reg = <0x0 0x600>; reg = <0x0 0x600>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_600>; next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache { L2_600: l2-cache {
compatible = "cache"; compatible = "cache";
next-level-cache = <&L3_0>; next-level-cache = <&L3_0>;
@ -132,6 +139,7 @@ CPU7: cpu@700 {
reg = <0x0 0x700>; reg = <0x0 0x700>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_700>; next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 2>;
L2_700: l2-cache { L2_700: l2-cache {
compatible = "cache"; compatible = "cache";
next-level-cache = <&L3_0>; next-level-cache = <&L3_0>;
@ -788,6 +796,19 @@ rpmhpd_opp_turbo_l1: opp10 {
}; };
}; };
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0 0x18591000 0 0x1000>,
<0 0x18592000 0 0x1000>,
<0 0x18593000 0 0x1000>;
reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
};
ufs_mem_hc: ufshc@1d84000 { ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8350-ufshc", "qcom,ufshc", compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
"jedec,ufs-2.0"; "jedec,ufs-2.0";