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ath9k_hw: change the way we initialize the pll for ar9271

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We adjust the core clock for ar9271 to 117 MHz; this also
requires us to adjust the baud divider based on the targetted
baud rate.

Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Luis R. Rodriguez 2009-10-19 02:33:34 -04:00 committed by John W. Linville
parent 8564328d85
commit c75724d174
2 changed files with 39 additions and 0 deletions
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36
drivers/net/wireless/ath/ath9k/hw.c
View File

@ -1040,6 +1040,22 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
} }
static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
{
u32 lcr;
u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
lcr = REG_READ(ah , 0x5100c);
lcr |= 0x80;
REG_WRITE(ah, 0x5100c, lcr);
REG_WRITE(ah, 0x51004, (baud_divider >> 8));
REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
lcr &= ~0x80;
REG_WRITE(ah, 0x5100c, lcr);
}
static void ath9k_hw_init_pll(struct ath_hw *ah, static void ath9k_hw_init_pll(struct ath_hw *ah,
struct ath9k_channel *chan) struct ath9k_channel *chan)
{ {
@ -1103,6 +1119,26 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
} }
REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
/* Switch the core clock for ar9271 to 117Mhz */
if (AR_SREV_9271(ah)) {
if ((pll == 0x142c) || (pll == 0x2850) ) {
udelay(500);
/* set CLKOBS to output AHB clock */
REG_WRITE(ah, 0x7020, 0xe);
/*
* 0x304: 117Mhz, ahb_ratio: 1x1
* 0x306: 40Mhz, ahb_ratio: 1x1
*/
REG_WRITE(ah, 0x50040, 0x304);
/*
* makes adjustments for the baud dividor to keep the
* targetted baud rate based on the used core clock.
*/
ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
AR9271_TARGET_BAUD_RATE);
}
}
udelay(RTC_PLL_SETTLE_DELAY); udelay(RTC_PLL_SETTLE_DELAY);
REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);

3
drivers/net/wireless/ath/ath9k/reg.h
View File

@ -1704,4 +1704,7 @@ enum {
#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24)
#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28)
#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
#endif #endif