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scsi: mpt3sas: Reload SBR without rebooting HBA
Add a new IOCTL command MPT3ENABLEDIAGSBRRELOAD. As a part of firmware update operation, applications use this IOCTL command to set the SBR reload bit in the Host Diagnostic register. This permits HBA firmware to be updated without powercycling the system. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202312280909.MZyhxwBL-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202312281141.jDyPezRn-lkp@intel.com/ Signed-off-by: Ranjan Kumar <ranjan.kumar@broadcom.com> Link: https://lore.kernel.org/r/20231228114810.11923-2-ranjan.kumar@broadcom.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Ranjan Kumar
Martin K. Petersen
parent
10a39667a1
commit
c0767560b0
@ -5481,7 +5481,7 @@ mpt3sas_atto_validate_nvram(struct MPT3SAS_ADAPTER *ioc,
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* mpt3sas_atto_get_sas_addr - get the ATTO SAS address from mfg page 1
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*
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* @ioc : per adapter object
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* @*sas_addr : return sas address
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* @sas_addr : return sas address
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* Return: 0 for success, non-zero for failure.
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*/
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static int
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@ -7913,6 +7913,67 @@ mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
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mutex_unlock(&ioc->base_cmds.mutex);
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}
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/**
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* mpt3sas_base_unlock_and_get_host_diagnostic- enable Host Diagnostic Register writes
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* @ioc: per adapter object
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* @host_diagnostic: host diagnostic register content
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*
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* Return: 0 for success, non-zero for failure.
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*/
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int
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mpt3sas_base_unlock_and_get_host_diagnostic(struct MPT3SAS_ADAPTER *ioc,
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u32 *host_diagnostic)
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{
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u32 count;
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*host_diagnostic = 0;
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count = 0;
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do {
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/* Write magic sequence to WriteSequence register
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* Loop until in diagnostic mode
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*/
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drsprintk(ioc, ioc_info(ioc, "write magic sequence\n"));
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writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
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writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
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writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
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writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
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writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
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writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
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writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
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/* wait 100 msec */
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msleep(100);
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if (count++ > 20) {
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ioc_info(ioc,
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"Stop writing magic sequence after 20 retries\n");
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_base_dump_reg_set(ioc);
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return -EFAULT;
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}
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*host_diagnostic = ioc->base_readl_ext_retry(&ioc->chip->HostDiagnostic);
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drsprintk(ioc,
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ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
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count, *host_diagnostic));
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} while ((*host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
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return 0;
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}
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/**
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* mpt3sas_base_lock_host_diagnostic: Disable Host Diagnostic Register writes
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* @ioc: per adapter object
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*/
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void
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mpt3sas_base_lock_host_diagnostic(struct MPT3SAS_ADAPTER *ioc)
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{
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drsprintk(ioc, ioc_info(ioc, "disable writes to the diagnostic register\n"));
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writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
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}
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/**
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* _base_diag_reset - the "big hammer" start of day reset
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* @ioc: per adapter object
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@ -7933,49 +7994,21 @@ _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
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drsprintk(ioc, ioc_info(ioc, "clear interrupts\n"));
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count = 0;
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do {
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/* Write magic sequence to WriteSequence register
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* Loop until in diagnostic mode
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*/
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drsprintk(ioc, ioc_info(ioc, "write magic sequence\n"));
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writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
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writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
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writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
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writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
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writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
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writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
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writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
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/* wait 100 msec */
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msleep(100);
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if (count++ > 20) {
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ioc_info(ioc,
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"Stop writing magic sequence after 20 retries\n");
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_base_dump_reg_set(ioc);
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goto out;
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}
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host_diagnostic = ioc->base_readl_ext_retry(&ioc->chip->HostDiagnostic);
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drsprintk(ioc,
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ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
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count, host_diagnostic));
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} while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
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mutex_lock(&ioc->hostdiag_unlock_mutex);
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if (mpt3sas_base_unlock_and_get_host_diagnostic(ioc, &host_diagnostic))
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goto out;
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hcb_size = ioc->base_readl(&ioc->chip->HCBSize);
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drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n"));
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writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
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&ioc->chip->HostDiagnostic);
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/*This delay allows the chip PCIe hardware time to finish reset tasks*/
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/* This delay allows the chip PCIe hardware time to finish reset tasks */
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msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
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/* Approximately 300 second max wait */
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for (count = 0; count < (300000000 /
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MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
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MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
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host_diagnostic = ioc->base_readl_ext_retry(&ioc->chip->HostDiagnostic);
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@ -7988,13 +8021,15 @@ _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
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if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
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break;
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msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
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/* Wait to pass the second read delay window */
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msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC/1000);
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}
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if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
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drsprintk(ioc,
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ioc_info(ioc, "restart the adapter assuming the HCB Address points to good F/W\n"));
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ioc_info(ioc, "restart the adapter assuming the\n"
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"HCB Address points to good F/W\n"));
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host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
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host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
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writel(host_diagnostic, &ioc->chip->HostDiagnostic);
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@ -8008,9 +8043,8 @@ _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
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writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
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&ioc->chip->HostDiagnostic);
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drsprintk(ioc,
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ioc_info(ioc, "disable writes to the diagnostic register\n"));
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writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
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mpt3sas_base_lock_host_diagnostic(ioc);
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mutex_unlock(&ioc->hostdiag_unlock_mutex);
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drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n"));
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ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
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@ -8028,6 +8062,7 @@ _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
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out:
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pci_cfg_access_unlock(ioc->pdev);
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ioc_err(ioc, "diag reset: FAILED\n");
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mutex_unlock(&ioc->hostdiag_unlock_mutex);
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return -EFAULT;
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}
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@ -1366,6 +1366,7 @@ struct MPT3SAS_ADAPTER {
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u8 got_task_abort_from_ioctl;
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struct mutex reset_in_progress_mutex;
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struct mutex hostdiag_unlock_mutex;
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spinlock_t ioc_reset_in_progress_lock;
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u8 ioc_link_reset_in_progress;
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@ -1790,6 +1791,9 @@ void mpt3sas_base_disable_msix(struct MPT3SAS_ADAPTER *ioc);
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int mpt3sas_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
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void mpt3sas_base_pause_mq_polling(struct MPT3SAS_ADAPTER *ioc);
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void mpt3sas_base_resume_mq_polling(struct MPT3SAS_ADAPTER *ioc);
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int mpt3sas_base_unlock_and_get_host_diagnostic(struct MPT3SAS_ADAPTER *ioc,
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u32 *host_diagnostic);
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void mpt3sas_base_lock_host_diagnostic(struct MPT3SAS_ADAPTER *ioc);
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/* scsih shared API */
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struct scsi_cmnd *mpt3sas_scsih_scsi_lookup_get(struct MPT3SAS_ADAPTER *ioc,
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@ -2543,6 +2543,56 @@ _ctl_addnl_diag_query(struct MPT3SAS_ADAPTER *ioc, void __user *arg)
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return 0;
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}
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/**
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* _ctl_enable_diag_sbr_reload - enable sbr reload bit
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* @ioc: per adapter object
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* @arg: user space buffer containing ioctl content
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*
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* Enable the SBR reload bit
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*/
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static int
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_ctl_enable_diag_sbr_reload(struct MPT3SAS_ADAPTER *ioc, void __user *arg)
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{
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u32 ioc_state, host_diagnostic;
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if (ioc->shost_recovery ||
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ioc->pci_error_recovery || ioc->is_driver_loading ||
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ioc->remove_host)
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return -EAGAIN;
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ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
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if (ioc_state != MPI2_IOC_STATE_OPERATIONAL)
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return -EFAULT;
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host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
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if (host_diagnostic & MPI2_DIAG_SBR_RELOAD)
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return 0;
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if (mutex_trylock(&ioc->hostdiag_unlock_mutex)) {
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if (mpt3sas_base_unlock_and_get_host_diagnostic(ioc, &host_diagnostic)) {
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mutex_unlock(&ioc->hostdiag_unlock_mutex);
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return -EFAULT;
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}
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} else
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return -EAGAIN;
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host_diagnostic |= MPI2_DIAG_SBR_RELOAD;
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writel(host_diagnostic, &ioc->chip->HostDiagnostic);
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host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
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mpt3sas_base_lock_host_diagnostic(ioc);
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mutex_unlock(&ioc->hostdiag_unlock_mutex);
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if (!(host_diagnostic & MPI2_DIAG_SBR_RELOAD)) {
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ioc_err(ioc, "%s: Failed to set Diag SBR Reload Bit\n", __func__);
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return -EFAULT;
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}
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ioc_info(ioc, "%s: Successfully set the Diag SBR Reload Bit\n", __func__);
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return 0;
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}
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#ifdef CONFIG_COMPAT
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/**
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* _ctl_compat_mpt_command - convert 32bit pointers to 64bit.
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@ -2719,6 +2769,10 @@ _ctl_ioctl_main(struct file *file, unsigned int cmd, void __user *arg,
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if (_IOC_SIZE(cmd) == sizeof(struct mpt3_addnl_diag_query))
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ret = _ctl_addnl_diag_query(ioc, arg);
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break;
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case MPT3ENABLEDIAGSBRRELOAD:
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if (_IOC_SIZE(cmd) == sizeof(struct mpt3_enable_diag_sbr_reload))
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ret = _ctl_enable_diag_sbr_reload(ioc, arg);
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break;
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default:
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dctlprintk(ioc,
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ioc_info(ioc, "unsupported ioctl opcode(0x%08x)\n",
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@ -98,6 +98,8 @@
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struct mpt3_diag_read_buffer)
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#define MPT3ADDNLDIAGQUERY _IOWR(MPT3_MAGIC_NUMBER, 32, \
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struct mpt3_addnl_diag_query)
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#define MPT3ENABLEDIAGSBRRELOAD _IOWR(MPT3_MAGIC_NUMBER, 33, \
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struct mpt3_enable_diag_sbr_reload)
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/* Trace Buffer default UniqueId */
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#define MPT2DIAGBUFFUNIQUEID (0x07075900)
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@ -448,4 +450,12 @@ struct mpt3_addnl_diag_query {
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uint32_t reserved2[2];
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};
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/**
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* struct mpt3_enable_diag_sbr_reload - enable sbr reload
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* @hdr - generic header
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*/
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struct mpt3_enable_diag_sbr_reload {
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struct mpt3_ioctl_header hdr;
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};
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#endif /* MPT3SAS_CTL_H_INCLUDED */
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@ -12240,6 +12240,7 @@ _scsih_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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/* misc semaphores and spin locks */
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mutex_init(&ioc->reset_in_progress_mutex);
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mutex_init(&ioc->hostdiag_unlock_mutex);
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/* initializing pci_access_mutex lock */
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mutex_init(&ioc->pci_access_mutex);
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spin_lock_init(&ioc->ioc_reset_in_progress_lock);
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