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ARM: dts: qcom-sdx55: switch PCIe QMP PHY to new style of bindings

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Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-19-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Dmitry Baryshkov 2023-08-20 17:20:35 +03:00 committed by Bjorn Andersson
parent 0bb80ecc33
commit bb56cff4ac
1 changed files with 12 additions and 19 deletions
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31
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
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@ -379,7 +379,7 @@ pcie_rc: pcie@1c00000 {
power-domains = <&gcc PCIE_GDSC>;
phys = <&pcie_lane>;
phys = <&pcie_phy>;
phy-names = "pciephy";
status = "disabled";
@ -428,7 +428,7 @@ pcie_ep: pcie-ep@1c00000 {
resets = <&gcc GCC_PCIE_BCR>;
reset-names = "core";
power-domains = <&gcc PCIE_GDSC>;
phys = <&pcie_lane>;
phys = <&pcie_phy>;
phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
@ -438,18 +438,25 @@ pcie_ep: pcie-ep@1c00000 {
pcie_phy: phy@1c07000 {
compatible = "qcom,sdx55-qmp-pcie-phy";
reg = <0x01c07000 0x1c4>;
reg = <0x01c07000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
<&gcc GCC_PCIE_RCHNG_PHY_CLK>;
<&gcc GCC_PCIE_RCHNG_PHY_CLK>,
<&gcc GCC_PCIE_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen";
"refgen",
"pipe";
clock-output-names = "pcie_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_PHY_BCR>;
reset-names = "phy";
@ -458,20 +465,6 @@ pcie_phy: phy@1c07000 {
assigned-clock-rates = <100000000>;
status = "disabled";
pcie_lane: lanes@1c06000 {
reg = <0x01c06000 0x104>, /* tx0 */
<0x01c06200 0x328>, /* rx0 */
<0x01c07200 0x1e8>, /* pcs */
<0x01c06800 0x104>, /* tx1 */
<0x01c06a00 0x328>, /* rx1 */
<0x01c07600 0x800>; /* pcs_misc */
clocks = <&gcc GCC_PCIE_PIPE_CLK>;
clock-names = "pipe0";
#phy-cells = <0>;
clock-output-names = "pcie_pipe_clk";
};
};
ipa: ipa@1e40000 {