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interconnect: qcom: sc8280xp: Drop IP0 interconnects
Similar to the sdx55 and sc7180, let's drop the MASTER_IPA_CORE and SLAVE_IPA_CORE interconnects for this platform. There are no actual users of this interconnect. The IP0 resource will be handled by clk-rpmh driver. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230109002935.244320-8-dmitry.baryshkov@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
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@ -284,15 +284,6 @@ static struct qcom_icc_node xm_ufs_card = {
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.links = { SC8280XP_SLAVE_A2NOC_SNOC },
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.links = { SC8280XP_SLAVE_A2NOC_SNOC },
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};
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};
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static struct qcom_icc_node ipa_core_master = {
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.name = "ipa_core_master",
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.id = SC8280XP_MASTER_IPA_CORE,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_IPA_CORE },
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};
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static struct qcom_icc_node qup0_core_master = {
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static struct qcom_icc_node qup0_core_master = {
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.name = "qup0_core_master",
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.name = "qup0_core_master",
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.id = SC8280XP_MASTER_QUP_CORE_0,
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.id = SC8280XP_MASTER_QUP_CORE_0,
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@ -882,13 +873,6 @@ static struct qcom_icc_node srvc_aggre2_noc = {
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.buswidth = 4,
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.buswidth = 4,
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};
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};
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static struct qcom_icc_node ipa_core_slave = {
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.name = "ipa_core_slave",
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.id = SC8280XP_SLAVE_IPA_CORE,
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.channels = 1,
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.buswidth = 8,
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};
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static struct qcom_icc_node qup0_core_slave = {
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static struct qcom_icc_node qup0_core_slave = {
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.name = "qup0_core_slave",
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.name = "qup0_core_slave",
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.id = SC8280XP_SLAVE_QUP_CORE_0,
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.id = SC8280XP_SLAVE_QUP_CORE_0,
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@ -1845,12 +1829,6 @@ static struct qcom_icc_bcm bcm_cn3 = {
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},
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},
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};
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};
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static struct qcom_icc_bcm bcm_ip0 = {
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.name = "IP0",
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.num_nodes = 1,
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.nodes = { &ipa_core_slave },
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};
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static struct qcom_icc_bcm bcm_mc0 = {
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static struct qcom_icc_bcm bcm_mc0 = {
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.name = "MC0",
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.name = "MC0",
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.keepalive = true,
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.keepalive = true,
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@ -2077,18 +2055,15 @@ static const struct qcom_icc_desc sc8280xp_aggre2_noc = {
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};
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};
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static struct qcom_icc_bcm * const clk_virt_bcms[] = {
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static struct qcom_icc_bcm * const clk_virt_bcms[] = {
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&bcm_ip0,
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&bcm_qup0,
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&bcm_qup0,
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&bcm_qup1,
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&bcm_qup1,
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&bcm_qup2,
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&bcm_qup2,
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};
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};
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static struct qcom_icc_node * const clk_virt_nodes[] = {
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static struct qcom_icc_node * const clk_virt_nodes[] = {
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[MASTER_IPA_CORE] = &ipa_core_master,
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[MASTER_QUP_CORE_0] = &qup0_core_master,
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[MASTER_QUP_CORE_0] = &qup0_core_master,
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[MASTER_QUP_CORE_1] = &qup1_core_master,
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[MASTER_QUP_CORE_1] = &qup1_core_master,
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[MASTER_QUP_CORE_2] = &qup2_core_master,
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[MASTER_QUP_CORE_2] = &qup2_core_master,
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[SLAVE_IPA_CORE] = &ipa_core_slave,
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[SLAVE_QUP_CORE_0] = &qup0_core_slave,
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[SLAVE_QUP_CORE_0] = &qup0_core_slave,
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[SLAVE_QUP_CORE_1] = &qup1_core_slave,
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[SLAVE_QUP_CORE_1] = &qup1_core_slave,
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[SLAVE_QUP_CORE_2] = &qup2_core_slave,
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[SLAVE_QUP_CORE_2] = &qup2_core_slave,
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@ -10,7 +10,7 @@
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#define SC8280XP_MASTER_PCIE_TCU 1
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#define SC8280XP_MASTER_PCIE_TCU 1
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#define SC8280XP_MASTER_SYS_TCU 2
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#define SC8280XP_MASTER_SYS_TCU 2
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#define SC8280XP_MASTER_APPSS_PROC 3
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#define SC8280XP_MASTER_APPSS_PROC 3
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#define SC8280XP_MASTER_IPA_CORE 4
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/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
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#define SC8280XP_MASTER_LLCC 5
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#define SC8280XP_MASTER_LLCC 5
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#define SC8280XP_MASTER_CNOC_LPASS_AG_NOC 6
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#define SC8280XP_MASTER_CNOC_LPASS_AG_NOC 6
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#define SC8280XP_MASTER_CDSP_NOC_CFG 7
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#define SC8280XP_MASTER_CDSP_NOC_CFG 7
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@ -84,7 +84,7 @@
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#define SC8280XP_MASTER_USB4_0 75
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#define SC8280XP_MASTER_USB4_0 75
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#define SC8280XP_MASTER_USB4_1 76
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#define SC8280XP_MASTER_USB4_1 76
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#define SC8280XP_SLAVE_EBI1 512
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#define SC8280XP_SLAVE_EBI1 512
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#define SC8280XP_SLAVE_IPA_CORE 513
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/* 513 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
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#define SC8280XP_SLAVE_AHB2PHY_0 514
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#define SC8280XP_SLAVE_AHB2PHY_0 514
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#define SC8280XP_SLAVE_AHB2PHY_1 515
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#define SC8280XP_SLAVE_AHB2PHY_1 515
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#define SC8280XP_SLAVE_AHB2PHY_2 516
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#define SC8280XP_SLAVE_AHB2PHY_2 516
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