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arm64: dts: rockchip: Add hdmi for rk3576

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Add hdmi and it's phy dt node for rk3576.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20241231095728.253943-3-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Andy Yan 2024-12-31 17:57:19 +08:00 committed by Heiko Stuebner
parent d74b842cab
commit ad0ea230ab
1 changed files with 58 additions and 0 deletions
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58
arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@ -625,6 +625,11 @@ u2phy1_otg: otg-port {
};
};
hdptxphy_grf: syscon@26032000 {
compatible = "rockchip,rk3576-hdptxphy-grf", "syscon";
reg = <0x0 0x26032000 0x0 0x100>;
};
vo1_grf: syscon@26036000 {
compatible = "rockchip,rk3576-vo1-grf", "syscon";
reg = <0x0 0x26036000 0x0 0x100>;
@ -1005,6 +1010,46 @@ vop_mmu: iommu@27d07e00 {
status = "disabled";
};
hdmi: hdmi@27da0000 {
compatible = "rockchip,rk3576-dw-hdmi-qp";
reg = <0x0 0x27da0000 0x0 0x20000>;
clocks = <&cru PCLK_HDMITX0>,
<&cru CLK_HDMITX0_EARC>,
<&cru CLK_HDMITX0_REF>,
<&cru MCLK_SAI6_8CH>,
<&cru CLK_HDMITXHDP>,
<&cru HCLK_VO0_ROOT>;
clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "avp", "cec", "earc", "main", "hpd";
phys = <&hdptxphy>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>;
power-domains = <&power RK3576_PD_VO0>;
resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>;
reset-names = "ref", "hdp";
rockchip,grf = <&ioc_grf>;
rockchip,vo-grf = <&vo0_grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in: port@0 {
reg = <0>;
};
hdmi_out: port@1 {
reg = <1>;
};
};
};
qos_hdcp1: qos@27f02000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f02000 0x0 0x20>;
@ -1863,6 +1908,19 @@ usbdp_phy: phy@2b010000 {
status = "disabled";
};
hdptxphy: hdmiphy@2b000000 {
compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy";
reg = <0x0 0x2b000000 0x0 0x2000>;
clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>;
clock-names = "ref", "apb";
resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>,
<&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>;
reset-names = "apb", "init", "cmn", "lane";
rockchip,grf = <&hdptxphy_grf>;
#phy-cells = <0>;
status = "disabled";
};
sram: sram@3ff88000 {
compatible = "mmio-sram";
reg = <0x0 0x3ff88000 0x0 0x78000>;