mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support
Add Retronix R-Car V4H Sparrow Hawk board based on Renesas R-Car V4H ES3.0 (R8A779G3) SoC. This is a single-board computer with single gigabit ethernet, DSI-to-eDP bridge, DSI and two CSI2 interfaces, audio codec, two CANFD ports, micro SD card slot, USB PD supply, USB 3.0 ports, M.2 Key-M slot for NVMe SSD, debug UART and JTAG. Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250420173829.200553-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Marek Vasut
Geert Uytterhoeven
parent
4c5e0f0c89
commit
a719915e76
@ -94,6 +94,10 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single.dtb
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r8a779g2-white-hawk-single-ard-audio-da7212-dtbs := r8a779g2-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo
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dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single-ard-audio-da7212.dtb
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dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk.dtb
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r8a779g3-sparrow-hawk-fan-pwm-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-pwm.dtbo
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dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtb
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dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single.dtb
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r8a779g3-white-hawk-single-ard-audio-da7212-dtbs := r8a779g3-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo
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dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single-ard-audio-da7212.dtb
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@ -0,0 +1,43 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Overlay for the PWM controlled blower fan in connector J3:FAN
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* on R-Car V4H ES3.0 Sparrow Hawk board
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*
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* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
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*
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* Example usage:
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*
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* # Localize hwmon sysfs directory that matches the PWM fan,
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* # enable the PWM fan, and configure the fan speed manually.
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* r8a779g3-sparrow-hawk$ grep -H . /sys/class/hwmon/hwmon?/name
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* /sys/class/hwmon/hwmon0/name:sensor1_thermal
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* /sys/class/hwmon/hwmon1/name:sensor2_thermal
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* /sys/class/hwmon/hwmon2/name:sensor3_thermal
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* /sys/class/hwmon/hwmon3/name:sensor4_thermal
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* /sys/class/hwmon/hwmon4/name:pwmfan
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* ^ ^^^^^^
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*
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* # Select mode 2 , enable fan PWM and regulator and keep them enabled.
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* # For details, see Linux Documentation/hwmon/pwm-fan.rst
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* r8a779g3-sparrow-hawk$ echo 2 > /sys/class/hwmon/hwmon4/pwm1_enable
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*
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* # Configure PWM fan speed in range 0..255 , 0 is stopped , 255 is full speed .
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* # Fan speed 101 is about 2/5 of the PWM fan speed:
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* r8a779g3-sparrow-hawk$ echo 101 > /sys/class/hwmon/hwmon4/pwm1
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*/
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/dts-v1/;
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/plugin/;
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/*
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* Override default PWM fan settings. For a list of available properties,
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* see schema Documentation/devicetree/bindings/hwmon/pwm-fan.yaml .
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*/
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&fan {
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/* Available cooling levels */
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cooling-levels = <0 50 100 150 200 255>;
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/* Four pulses of tacho signal per one revolution */
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pulses-per-revolution = <4>;
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/* PWM period: 100us ~= 10 kHz */
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pwms = <&pwm0 0 100000>;
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};
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666
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
Normal file
666
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
Normal file
@ -0,0 +1,666 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the R-Car V4H ES3.0 Sparrow Hawk board
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*
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* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "r8a779g3.dtsi"
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/ {
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model = "Retronix Sparrow Hawk board based on r8a779g3";
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compatible = "retronix,sparrow-hawk", "renesas,r8a779g3",
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"renesas,r8a779g0";
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aliases {
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ethernet0 = &avb0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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serial0 = &hscif0;
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serial1 = &hscif1;
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serial2 = &hscif3;
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spi0 = &rpc;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
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stdout-path = "serial0:921600n8";
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};
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/* Page 31 / FAN */
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fan: pwm-fan {
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pinctrl-0 = <&irq4_pins>;
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pinctrl-names = "default";
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compatible = "pwm-fan";
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#cooling-cells = <2>;
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interrupts-extended = <&intc_ex 4 IRQ_TYPE_EDGE_FALLING>;
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/*
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* The fan model connected to this device can be selected
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* by user. Set "cooling-levels" DT property to single 255
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* entry to force the fan PWM into constant HIGH, which
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* forces the fan to spin at maximum RPM, thus providing
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* maximum cooling to this device and protection against
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* misconfigured PWM duty cycle to the fan.
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*
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* User has to configure "pwms" and "pulses-per-revolution"
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* DT properties according to fan datasheet first, and then
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* extend "cooling-levels = <0 m n ... 255>" property to
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* achieve proper fan control compatible with fan model
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* installed by user.
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*/
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cooling-levels = <255>;
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pulses-per-revolution = <2>;
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pwms = <&pwm0 0 50000>;
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};
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/*
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* Page 15 / LPDDR5
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*
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* This configuration listed below is for the 8 GiB board variant
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* with MT62F1G64D8EK-023 WT:C LPDDR5 part populated on the board.
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*
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* A variant with 16 GiB MT62F2G64D8EK-023 WT:C part populated on
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* the board is automatically handled by the bootloader, which
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* adjusts the correct DRAM size into the memory nodes below.
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*/
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x78000000>;
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};
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memory@480000000 {
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device_type = "memory";
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reg = <0x4 0x80000000 0x0 0x80000000>;
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};
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memory@600000000 {
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device_type = "memory";
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reg = <0x6 0x00000000 0x1 0x00000000>;
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};
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/* Page 27 / DSI to Display */
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mini-dp-con {
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compatible = "dp-connector";
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label = "CN6";
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type = "full-size";
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port {
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mini_dp_con_in: endpoint {
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remote-endpoint = <&sn65dsi86_out>;
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};
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};
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};
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reg_1p2v: regulator-1p2v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.2V";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* Page 27 / DSI to Display */
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sn65dsi86_refclk: clk-x9 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <38400000>;
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};
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/* Page 17 uSD-Slot */
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vcc_sdhi: regulator-vcc-sdhi {
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compatible = "regulator-gpio";
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regulator-name = "SDHI VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 0>, <1800000 1>;
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};
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};
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/* Page 22 / Ether_AVB0 */
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&avb0 {
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pinctrl-0 = <&avb0_pins>;
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pinctrl-names = "default";
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phy-handle = <&avb0_phy>;
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tx-internal-delay-ps = <2000>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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avb0_phy: ethernet-phy@0 { /* KSZ9031RNXVB */
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compatible = "ethernet-phy-id0022.1622",
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"ethernet-phy-ieee802.3-c22";
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rxc-skew-ps = <1500>;
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reg = <0>;
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/* AVB0_PHY_INT_V */
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interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>;
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/* GP7_10/AVB0_RESETN_V */
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reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <300>;
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};
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};
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};
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/* Page 28 / CANFD_IF */
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&can_clk {
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clock-frequency = <40000000>;
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};
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/* Page 28 / CANFD_IF */
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&canfd {
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pinctrl-0 = <&canfd3_pins>, <&canfd4_pins>, <&can_clk_pins>;
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pinctrl-names = "default";
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status = "okay";
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channel3 {
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status = "okay";
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};
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channel4 {
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status = "okay";
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};
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};
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/* Page 27 / DSI to Display */
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&dsi1 {
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status = "okay";
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ports {
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port@1 {
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dsi1_out: endpoint {
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remote-endpoint = <&sn65dsi86_in>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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};
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/* Page 27 / DSI to Display */
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&du {
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status = "okay";
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};
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/* Page 5 / R-Car V4H_INT_I2C */
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&extal_clk { /* X3 */
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clock-frequency = <16666666>;
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};
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/* Page 5 / R-Car V4H_INT_I2C */
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&extalr_clk { /* X2 */
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clock-frequency = <32768>;
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};
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/* Page 26 / 2230 Key M M.2 */
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&gpio4 {
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/* 9FGV0441 nOE inputs 0 and 1 */
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pcie-m2-oe-hog {
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gpio-hog;
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gpios = <21 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "PCIe-CLK-nOE-M2";
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};
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/* 9FGV0441 nOE inputs 2 and 3 */
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pcie-usb-oe-hog {
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gpio-hog;
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gpios = <22 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "PCIe-CLK-nOE-USB";
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};
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};
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/* Page 23 / DEBUG */
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&hscif0 { /* FTDI ADBUS[3:0] */
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pinctrl-0 = <&hscif0_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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bootph-all;
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status = "okay";
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};
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/* Page 23 / DEBUG */
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&hscif1 { /* FTDI BDBUS[3:0] */
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pinctrl-0 = <&hscif1_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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/* Page 24 / UART */
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&hscif3 { /* CN7 pins 8 (TX) and 10 (RX) */
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pinctrl-0 = <&hscif3_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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/* Page 24 / I2C SWITCH */
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&i2c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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mux@71 {
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compatible = "nxp,pca9544"; /* TCA9544 */
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reg = <0x71>;
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#address-cells = <1>;
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#size-cells = <0>;
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vdd-supply = <®_3p3v>;
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i2c0_mux0: i2c@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Page 27 / DSI to Display */
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bridge@2c {
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pinctrl-0 = <&irq0_pins>;
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pinctrl-names = "default";
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compatible = "ti,sn65dsi86";
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reg = <0x2c>;
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clocks = <&sn65dsi86_refclk>;
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clock-names = "refclk";
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interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>;
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enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
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vccio-supply = <®_1p8v>;
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vpll-supply = <®_1p8v>;
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vcca-supply = <®_1p2v>;
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vcc-supply = <®_1p2v>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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sn65dsi86_in: endpoint {
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remote-endpoint = <&dsi1_out>;
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};
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};
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port@1 {
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reg = <1>;
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sn65dsi86_out: endpoint {
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remote-endpoint = <&mini_dp_con_in>;
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};
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};
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};
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};
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};
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i2c0_mux1: i2c@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c0_mux2: i2c@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c0_mux3: i2c@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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/* Page 29 / CSI_IF_CN / CAM_CN0 */
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&i2c1 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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};
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/* Page 29 / CSI_IF_CN / CAM_CN1 */
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&i2c2 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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};
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/* Page 31 / IO_CN */
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&i2c3 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c3_pins>;
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pinctrl-names = "default";
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};
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/* Page 31 / IO_CN */
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&i2c4 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c4_pins>;
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pinctrl-names = "default";
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};
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/* Page 18 / POWER_CORE and Page 19 / POWER_PMIC */
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&i2c5 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c5_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
/* Page 17 uSD-Slot */
|
||||
&mmc0 {
|
||||
pinctrl-0 = <&sd_pins>;
|
||||
pinctrl-1 = <&sd_uhs_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; /* SD_CD */
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <&vcc_sdhi>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Page 26 / 2230 Key M M.2 */
|
||||
&pcie0_clkref {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&pciec0 {
|
||||
reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Page 25 / PCIe to USB */
|
||||
&pcie1_clkref {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&pciec1 {
|
||||
/* uPD720201 is PCIe Gen2 x1 device */
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Page 22 / Ether_AVB0 */
|
||||
avb0_pins: avb0 {
|
||||
mux {
|
||||
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
|
||||
"avb0_txcrefclk";
|
||||
function = "avb0";
|
||||
};
|
||||
|
||||
pins-mdio {
|
||||
groups = "avb0_mdio";
|
||||
drive-strength = <21>;
|
||||
};
|
||||
|
||||
pins-mii {
|
||||
groups = "avb0_rgmii";
|
||||
drive-strength = <21>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/* Page 28 / CANFD_IF */
|
||||
can_clk_pins: can-clk {
|
||||
groups = "can_clk";
|
||||
function = "can_clk";
|
||||
};
|
||||
|
||||
/* Page 28 / CANFD_IF */
|
||||
canfd3_pins: canfd3 {
|
||||
groups = "canfd3_data";
|
||||
function = "canfd3";
|
||||
};
|
||||
|
||||
/* Page 28 / CANFD_IF */
|
||||
canfd4_pins: canfd4 {
|
||||
groups = "canfd4_data";
|
||||
function = "canfd4";
|
||||
};
|
||||
|
||||
/* Page 23 / DEBUG */
|
||||
hscif0_pins: hscif0 {
|
||||
groups = "hscif0_data", "hscif0_ctrl";
|
||||
function = "hscif0";
|
||||
};
|
||||
|
||||
/* Page 23 / DEBUG */
|
||||
hscif1_pins: hscif1 {
|
||||
groups = "hscif1_data_a", "hscif1_ctrl_a";
|
||||
function = "hscif1";
|
||||
};
|
||||
|
||||
/* Page 24 / UART */
|
||||
hscif3_pins: hscif3 {
|
||||
groups = "hscif3_data_a";
|
||||
function = "hscif3";
|
||||
};
|
||||
|
||||
/* Page 24 / I2C SWITCH */
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
/* Page 29 / CSI_IF_CN / CAM_CN0 */
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
/* Page 29 / CSI_IF_CN / CAM_CN1 */
|
||||
i2c2_pins: i2c2 {
|
||||
groups = "i2c2";
|
||||
function = "i2c2";
|
||||
};
|
||||
|
||||
/* Page 31 / IO_CN */
|
||||
i2c3_pins: i2c3 {
|
||||
groups = "i2c3";
|
||||
function = "i2c3";
|
||||
};
|
||||
|
||||
/* Page 31 / IO_CN */
|
||||
i2c4_pins: i2c4 {
|
||||
groups = "i2c4";
|
||||
function = "i2c4";
|
||||
};
|
||||
|
||||
/* Page 18 / POWER_CORE */
|
||||
i2c5_pins: i2c5 {
|
||||
groups = "i2c5";
|
||||
function = "i2c5";
|
||||
};
|
||||
|
||||
/* Page 27 / DSI to Display */
|
||||
irq0_pins: irq0 {
|
||||
groups = "intc_ex_irq0_a";
|
||||
function = "intc_ex";
|
||||
};
|
||||
|
||||
/* Page 31 / FAN */
|
||||
irq4_pins: irq4 {
|
||||
groups = "intc_ex_irq4_b";
|
||||
function = "intc_ex";
|
||||
};
|
||||
|
||||
/* Page 31 / FAN */
|
||||
pwm0_pins: pwm0 {
|
||||
groups = "pwm0";
|
||||
function = "pwm0";
|
||||
};
|
||||
|
||||
/* Page 31 / CN7 pin 12 */
|
||||
pwm1_pins: pwm1 {
|
||||
groups = "pwm1_b";
|
||||
function = "pwm1";
|
||||
};
|
||||
|
||||
/* Page 31 / CN7 pin 32 */
|
||||
pwm6_pins: pwm6 {
|
||||
groups = "pwm6";
|
||||
function = "pwm6";
|
||||
};
|
||||
|
||||
/* Page 31 / CN7 pin 33 */
|
||||
pwm7_pins: pwm7 {
|
||||
groups = "pwm7";
|
||||
function = "pwm7";
|
||||
};
|
||||
|
||||
/* Page 16 / QSPI_FLASH */
|
||||
qspi0_pins: qspi0 {
|
||||
groups = "qspi0_ctrl", "qspi0_data4";
|
||||
function = "qspi0";
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
/* Page 6 / SCIF_CLK_SOC_V */
|
||||
scif_clk_pins: scif-clk {
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
/* Page 17 uSD-Slot */
|
||||
sd_pins: sd {
|
||||
groups = "mmc_data4", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
/* Page 17 uSD-Slot */
|
||||
sd_uhs_pins: sd-uhs {
|
||||
groups = "mmc_data4", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
power-source = <1800>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Page 31 / FAN */
|
||||
&pwm0 {
|
||||
pinctrl-0 = <&pwm0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Page 31 / CN7 pin 12 */
|
||||
&pwm1 {
|
||||
pinctrl-0 = <&pwm1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Page 31 / CN7 pin 32 */
|
||||
&pwm6 {
|
||||
pinctrl-0 = <&pwm6_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Page 31 / CN7 pin 33 */
|
||||
&pwm7 {
|
||||
pinctrl-0 = <&pwm7_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Page 16 / QSPI_FLASH */
|
||||
&rpc {
|
||||
pinctrl-0 = <&qspi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
bootph-all;
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fs512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
bootph-all;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
boot@0 {
|
||||
reg = <0x0 0x1000000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
user@1000000 {
|
||||
reg = <0x1000000 0x2f80000>;
|
||||
};
|
||||
|
||||
env1@3f80000 {
|
||||
reg = <0x3f80000 0x40000>;
|
||||
};
|
||||
|
||||
env2@3fc0000 {
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Page 6 / SCIF_CLK_SOC_V */
|
||||
&scif_clk { /* X12 */
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user