Proxmox-Port/linux-loongson
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson synced 2025-09-11 11:08:24 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

wifi: rtw89: read version of analog hardware

Browse Source 
The chip contains digital and analog parts, and each of them has its own
version number. This is used by BT coexistence mechanism to make strategy
decision for different analog version.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230330133324.19538-2-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih 2023-03-30 21:33:21 +08:00 committed by Kalle Valo
parent 9f9882dbe2
commit a6fb2bb846
3 changed files with 13 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/net/wireless/realtek/rtw89/core.c
View File

@ -3535,6 +3535,8 @@ void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
int ret;
u8 val;
u8 cv;
cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK);
@ -3546,6 +3548,14 @@ static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
}
rtwdev->hal.cv = cv;
if (chip->chip_id == RTL8852B || chip->chip_id == RTL8851B) {
ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val);
if (!ret)
return;
rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK);
}
}
static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev)

2
drivers/net/wireless/realtek/rtw89/core.h
View File

@ -108,6 +108,7 @@ enum rtw89_core_chip_id {
RTL8852A,
RTL8852B,
RTL8852C,
RTL8851B,
};
enum rtw89_cv {
@ -3412,6 +3413,7 @@ struct rtw89_sub_entity {
struct rtw89_hal {
u32 rx_fltr;
u8 cv;
u8 acv;
u32 sw_amsdu_max_size;
u32 antenna_tx;
u32 antenna_rx;

1
drivers/net/wireless/realtek/rtw89/mac.h
View File

@ -1117,6 +1117,7 @@ enum rtw89_mac_xtal_si_offset {
XTAL_SI_XTAL_XMD_4 = 0x26,
#define XTAL_SI_LPS_CAP GENMASK(3, 0)
XTAL_SI_CV = 0x41,
#define XTAL_SI_ACV_MASK GENMASK(3, 0)
XTAL_SI_LOW_ADDR = 0x62,
#define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0)
XTAL_SI_CTRL = 0x63,